Patents by Inventor Gilad Merran

Gilad Merran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Error checking of a multi-threaded computer processor design under test
    Patent number: 10324815
    Abstract: Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Oz D. Hershkovitz, Gilad Merran, Eyal Naor
  • ERROR CHECKING OF A MULTI-THREADED COMPUTER PROCESSOR DESIGN UNDER TEST
    Publication number: 20180232292
    Abstract: Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.
    Type: Application
    Filed: February 14, 2017
    Publication date: August 16, 2018
    Inventors: Erez Barak, Oz D. Hershkovitz, Gilad Merran, Eyal Naor