Abstract: The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment of the invention comprises a method for performing position location on a subscriber unit in a terrestrial wireless telephone system using a set of satellites each transmitting a signal, the terrestrial wireless telephone system having base stations, including the steps of transmitting an aiding message from the base station to the subscriber unit, said aiding message containing information regarding a data boundary for each signal from the set of satellites, applying correlation codes to each signal yielding corresponding correlation data and accumulating said correlation data over an first interval preceding a corresponding data boundary yielding a first accumulation result, and a second interval following said corresponding data boundary yielding a second accumulation result.

Abstract: DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.

Abstract: The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment of the invention comprises a method for performing position location on a subscriber unit in a terrestrial wireless telephone system using a set of satellites each transmitting a signal, the terrestrial wireless telephone system having base stations, including the steps of transmitting an aiding message from the base station to the subscriber unit, said aiding message containing information regarding a data boundary for each signal from the set of satellites, applying correlation codes to each signal yielding corresponding correlation data and accumulating said correlation data over an first interval preceding a corresponding data boundary yielding a first accumulation result, and a second interval following said corresponding data boundary yielding a second accumulation result.

Abstract: A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions may, but are not required to, occur across memory word boundaries. Preferably, the variable length instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation (or operations) to be performed, thereby allowing multiple operations to be performed during each clock cycle. This reduces the total number of clock cycles necessary to perform a task.

Abstract: The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment of the invention comprises a method for performing position location on a subscriber unit in a terrestrial wireless telephone system using a set of satellites each transmitting a signal, the terrestrial wireless telephone system having base stations, including the steps of transmitting an aiding message from the base station to the subscriber unit, said aiding message containing information regarding a data boundary for each signal from the set of satellites, applying correlation codes to each signal yielding corresponding correlation data and accumulating said correlation data over an first interval preceding a corresponding data boundary yielding a first accumulation result, and a second interval following said corresponding data boundary yielding a second accumulation result.

Abstract: This disclosure is directed to techniques for estimating signal-to-noise ratio (SNR) of signals received by a wireless communication device. The techniques take advantage of spatial receive diversity in a wireless communication device to achieve accurate estimates of SNR. In general, a spatial projection wiener filter function can be applied to incoming symbol estimates to support efficient computation of SNR. The estimated SNR can be used to produce power control commands for use in forward power control.

Abstract: In general, the invention is directed toward a device for processing digital video data, such as an encoder, a decoder or an encoder/decoder (CODEC). The device makes use of an innovative architecture in which functionality is partitioned between an embedded processor, a digital signal processor and dedicated hardware to achieve increased performance. In addition, the device includes a programmable video direct memory access (VDMA) controller to retrieve video data from memory in response to a command specifying a multidimensional block of video data.

Abstract: This disclosure is directed to techniques for estimating signal-to-noise ratio (SNR) of signals received by a wireless communication device. The techniques take advantage of spatial receive diversity in a wireless communication device to achieve accurate estimates of SNR. In general, a spatial projection wiener filter function can be applied to incoming symbol estimates to support efficient computation of SNR. The estimated SNR can be used to produce power control commands for use in forward power control.

Abstract: According to a disclosed embodiment, a receiver comprising a digital rotator in combination with a frequency error discriminator in a digital automatic frequency control loop is used to arrive at accurate digital values used to calibrate a local oscillation frequency. A frequency error in the oscillation frequency of a local frequency generation loop causes a change in the baseband input signal frequency. The change in the baseband input signal frequency related to the frequency error in the local frequency generation loop can be detected as a phase rotation by the frequency error discriminator. By using the digital automatic frequency control loop, the frequency error introduced by the local frequency generation is determined with accuracy. The frequency error and corresponding control bits are entered into a calibration table. The calibration table may be used to adjust the local oscillation frequency for temperature changes, pilot frequency searching, and quick paging.

Abstract: A system for enhancing low frequency spectral content of a signal transmitted via a channel, that includes a noise suppression circuit to update channel energy estimates; and a spectral enhancer circuit coupled to and follows the noise suppression circuit, the spectral enhancer circuit to determine channel enhancement in response to the channel energy estimates.

Abstract: The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment of the invention comprises a method of performing position location in a wireless subscriber unit having a local oscillator, including the steps of receiving a position location request, acquiring a timing signal when a sufficient period of time has elapsed since the local oscillator has been corrected and correcting the local oscillator using a correction signal based on the timing signal, substantially freezing the correction signal, performing a position location procedure using the local oscillator with the correction signal applied, and ending said position location procedure.

Abstract: A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions may, but are not required to, occur across memory word boundaries. Preferably, the variable length instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation (or operations) to be performed, thereby allowing multiple operations to be performed during each clock cycle. This reduces the total number of clock cycles necessary to perform a task.

Abstract: A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories.

Abstract: A method and apparatus for frequency tracking is described. The present invention provides a tracking mechanism for removing the effects of error due to frequency offset as well as compensation for frequency error due to doppler in a plurality of multipath signals. Each finger of a RAKE receiver utilizing the present invention will compute a frequency error for that finger. The weighted average of all of these frequency errors is calculated and filtered to provide a control signal for varying the frequency of IF and RF frequency synthesizers, accounting for the common frequency offset seen at each finger. Additionally, each finger is equipped with a rotator for providing frequency adjustment specific to that finger. The frequency of each finger is adjusted through feedback of the frequency error for that finger.

Abstract: The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs, and DFTs. The architecture uses a coupled dual-MAC architecture (MAC1), (MAC2) and attaches a dual-MAC coprocessor (MAC3), (MAC4) onto it in a unique way to achieve a significant increase in processing capability.

Abstract: A novel and improved method for performing paging is described. In one embodiment of the invention a searcher is used to detect spread spectrum signals. Samples received RF signals are stored in a sample buffer. During standby mode, the samples are gathered during paging slots assigned to the mobile. A set of searches are performed on the samples, and if pilot signals are detected additional demodulation is performed to detect paging messages. The resulting set of demodulation data may be combined to increase detection. After a page message has been detected, additional demodulation resources may be activated to processes more complete page messages, or other information channels. In one embodiment of the invention, the searcher includes a demodulator to perform quick page detection without the use of finger elements to reduce idle mode power consumption.

Abstract: In general, the invention is directed toward a device for processing digital video data, such as an encoder, a decoder or an encoder/decoder (CODEC). The device makes use of an innovative architecture in which functionality is partitioned between an embedded processor, a digital signal processor and dedicated hardware to achieve increased performance. In addition, the device includes a programmable video direct memory access (VDMA) controller to retrieve video data from memory in response to a command specifying a multidimensional block of video data.

Abstract: Two multiply-accumulate units are coupled together so that the computation (B*C)+(D*E) can be completed in one cycle. An adder (216) adds together the products of the two multipliers (206), (208). The sum is applied to the first accumulator (220). Preferably, the second product is also applied to the second accumulator (222), and a multiplexer (218) applies either a zero or the second product to the adder (216). If two unrelated computations are to be executed simultaneously, then the zero is applied, and the output of the second accumulator is fed back to the register file (PI2). If a single (B*C)+(D*E) computation is to be executed, then the second product is applied to the adder, and the output of the second accumulator is disregarded.

Abstract: A velocity estimate is determined from a received signal by counting the number of times a signal in one multipath crosses a predetermined threshold in a given amount of time. A signal is received and a single multipath is extracted from the received signal. Instantaneous envelope values of the extracted multipath are calculated. A plurality of the instantaneous envelope values are used to calculate a running RMS value. A level crossing threshold is determined using the running RMS value. The number of times the instantaneous envelope value crosses the level crossing threshold is counted. The number of level crossings is mapped to a velocity estimate.

Abstract: A method and circuit for digital signal processing. The disclosed method and circuit uses a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory. The beginning and ending of instructions may occur across memory word boundaries. Instructions may contain variable numbers of instruction fragments that cause a particular operation to be performed. The disclosed circuit has a set of three data buses over which data may be exchanged with a register bank and three data memories. Data buses include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Additionally, the disclosed circuit has a register bank that is accessible by at least two processing units. The disclosed circuit further includes an instruction fetch unit that receives instructions of variable length stored in an instruction memory.