Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Abstract: A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

Abstract: This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.

Abstract: This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Abstract: A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

Abstract: A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

Abstract: The velocity of a wireless communications device (WCD) (106) is estimated. In response to this estimate a power control command rate is determined. The WCD 106 transmits power control signals to a base station (102) according to the power control command rate. The power control command rate may be determined by mapping the estimated velocity to a velocity range, and selecting a rate that corresponds to the velocity range as the power control command rate. Velocity is estimated by measuring a level crossing rate of a multipath signal.

Abstract: The velocity of a wireless communications device (106) is estimated. In response to this estimate, a filter bandwidth, such as a pilot filter (310) bandwidth, is adjusted so that the introduction of noise and distortion to a signal received by the device is mitigated. The filter bandwidth is adjusted by increasing it as the estimated velocity increases; and decreasing it as the estimated velocity decreases. Such adjustments may be accomplished through providing a number of predetermined bandwidths that each correspond to a particular velocity range, and setting the filter bandwidth to the predetermined bandwidth that corresponds to the estimated velocity.

Abstract: Techniques to acquire and track pilots in a CDMA system. In an aspect, frequency acquisition of a number of signal instances (i.e., multipaths) in a received signal may be achieved concurrently based on a frequency control loop (RAFC) maintained for each finger processor of a rake receiver. Upon successful acquisition, frequency tracking of acquired multipaths may be achieved based on a combination of a frequency control loop (VAFC) maintained for an oscillator used for downconverting the received signal and the RAFCs for the finger processors. In a tracking mode, the VAFC tracks the average frequency of the acquired multipaths by adjusting the frequency of the oscillator. The RAFC of each finger processor tracks the residual frequency error (e.g., due to Doppler frequency shift) of the individual acquired multipath by adjusting the frequency of a complex sinusoidal signal used in a rotator within the finger processor.

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Abstract: Techniques for scalable CDMA demodulation with maximum response latency are disclosed. In one aspect, a finger timing unit generates signals indicating cycle boundaries for a plurality of fingers, and an offline processing unit processes stored samples for those fingers in response to the signals. In another aspect, incoming samples are stored in a RAM, while finger timing is maintained using a plurality of counters. The RAM address is stored on symbol boundaries. Symbols for each finger are generated in an offline processing unit, clocked at a higher speed than the finger counters, from a RAM location computed using the stored RAM address. Various other aspects are also presented. These aspects provide for decoupling of the chip rate processing from chip time, which allows a single offline processing unit to service a plurality of fingers, thus reducing additional hardware required to support additional fingers while maintaining maximum latency requirements.

Abstract: Techniques to acquire pilots over code space and/or frequency errors. In one aspect, pilot acquisition is performed using a number of substages, and some of the substages are pipelined and performed in parallel using different processing elements. A searcher initially searches over a designated code space to find peaks, and these peaks may be re-evaluated. Finger processors then attempt to acquire the candidate peaks. The searcher may be operated to search for the next set of peaks while the finger processors process the current set of peaks. In another aspect, the full range of frequency errors for the pilots is divided into a number of frequency bins. A multi-stage scheme is used to evaluate the bins, and may employ pipelining and parallel processing such that a search for peaks in the next bin is performed while acquisition of peaks found for the current bin is attempted.

Abstract: This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.

Abstract: This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.

Abstract: The velocity of a wireless communications device (WCD) (106) is estimated. In response to this estimate a power control command rate is determined. The WCD 106 transmits power control signals to a base station (102) according to the power control command rate. The power control command rate may be determined by mapping the estimated velocity to a velocity range, and selecting a rate that corresponds to the velocity range as the power control command rate. Velocity is estimated by measuring a level crossing rate of a multipath signal.

Abstract: Techniques for scalable CDMA demodulation with maximum response latency are disclosed. In one aspect, a finger timing unit generates signals indicating cycle boundaries for a plurality of fingers, and an offline processing unit processes stored samples for those fingers in response to the signals. In another aspect, incoming samples are stored in a RAM, while finger timing is maintained using a plurality of counters. The RAM address is stored on symbol boundaries. Symbols for each finger are generated in an offline processing unit, clocked at a higher speed than the finger counters, from a RAM location computed using the stored RAM address. Various other aspects are also presented. These aspects provide for decoupling of the chip rate processing from chip time, which allows a single offline processing unit to service a plurality of fingers, thus reducing additional hardware required to support additional fingers while maintaining maximum latency requirements.

Abstract: Techniques to acquire pilots over code space and/or frequency errors. In one aspect, pilot acquisition is performed using a number of substages, and some of the substages are pipelined and performed in parallel using different processing elements. A searcher initially searches over a designated code space to find peaks, and these peaks may be re-evaluated. Finger processors then attempt to acquire the candidate peaks. The searcher may be operated to search for the next set of peaks while the finger processors process the current set of peaks. In another aspect, the full range of frequency errors for the pilots is divided into a number of frequency bins. A multi-stage scheme is used to evaluate the bins, and may employ pipelining and parallel processing such that a search for peaks in the next bin is performed while acquisition of peaks found for the current bin is attempted.

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.