Patents by Inventor Gilbert Meyer

Gilbert Meyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10787829
    Abstract: Systems, methods, and devices of the various embodiments may enable manufactured modular construction. The various embodiment manufactured modular construction systems, methods, and devices may offer a solution to the housing shortage worldwide that is less than half the cost of the cost of current modular buildings. Various embodiments may include interlocking vertical and horizontal elements. Various embodiments may include a locking system pulling upper horizontal elements of an embodiment modular building toward lower horizontal elements and/or a foundation or a lower floor of the embodiment modular building to thereby lock vertical elements and vertical panels in place between the upper horizontal elements and the lower horizontal elements, foundation, and/or lower floor. In various embodiments, the locking system may include a shock absorber.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 29, 2020
    Assignee: MMC-3 HOLDINGS, LLC
    Inventors: Gilbert Meyer, Ethan Wong
  • Patent number: 10783080
    Abstract: An interconnect system and method of operating the system are disclosed. A master device has access to a cache and a slave device has an associated data storage device for long-term storage of data items. The master device can initiate a cache maintenance operation in the interconnect system with respect to a data item temporarily stored in the cache causing action to be taken by the slave device with respect to storage of the data item in the data storage device. For long latency operations the master device can issue a separated cache maintenance request specifying the data item and the slave device. In response an intermediate device signals an acknowledgment response indicating that it has taken on responsibility for completion of the cache maintenance operation and issues the separated cache maintenance request to the slave device.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: September 22, 2020
    Assignee: ARM LIMITED
    Inventors: Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal, Paul Gilbert Meyer
  • Patent number: 10761987
    Abstract: An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 1, 2020
    Assignee: Arm Limited
    Inventors: Jamshed Jalal, Mark David Werkheiser, Michael Filippo, Klas Magnus Bruce, Paul Gilbert Meyer
  • Patent number: 10713187
    Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 14, 2020
    Assignee: ARM Limited
    Inventors: Michael Filippo, Jamshed Jalal, Klas Magnus Bruce, Paul Gilbert Meyer, David Joseph Hawkins, Phanindra Kumar Mannava, Joseph Michael Pusdesris
  • Patent number: 10698825
    Abstract: In a system-on-chip there is a local interconnect to connect local devices on the chip to one another, a gateway to connect the chip to a remote chip of a plurality of chips in a cache-coherent multi-chip system via an inter-chip interconnect, and a cache-coherent device. The cache-coherent device has a cache-coherency look-up table having entries for shared cache data lines. When a data access request is received via the inter-chip interconnect and the local interconnect a system-unique identifier for a request source of the data access request is generated in dependence on an inter-chip request source identifier used on the inter-chip interconnect and an identifier indicative of the remote chip. The bit-set used to express the system-unique identifier is larger than the bit-set used to express the inter-chip request source identifier.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: June 30, 2020
    Assignee: Arm Limited
    Inventors: Gurunath Ramagiri, Ashok Kumar Tummala, Mark David Werkheiser, Jamshed Jalal, Premkishore Shivakumar, Paul Gilbert Meyer
  • Publication number: 20200167284
    Abstract: An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: Jamshed JALAL, Mark David WERKHEISER, Michael FILIPPO, Klas Magnus BRUCE, Paul Gilbert MEYER
  • Publication number: 20200133865
    Abstract: An interconnect system and method of operating the system are disclosed. A master device has access to a cache and a slave device has an associated data storage device for long-term storage of data items. The master device can initiate a cache maintenance operation in the interconnect system with respect to a data item temporarily stored in the cache causing action to be taken by the slave device with respect to storage of the data item in the data storage device. For long latency operations the master device can issue a separated cache maintenance request specifying the data item and the slave device. In response an intermediate device signals an acknowledgment response indicating that it has taken on responsibility for completion of the cache maintenance operation and issues the separated cache maintenance request to the slave device.
    Type: Application
    Filed: October 29, 2018
    Publication date: April 30, 2020
    Inventors: Phanindra Kumar MANNAVA, Bruce James MATHEWSON, Jamshed JALAL, Paul Gilbert MEYER
  • Patent number: 10591977
    Abstract: A method, system, and device provide for selective control in a distributed cache system of the power state of a number of receiver partitions arranged in one or more partition groups. A power control element coupled to one or more of the receiver partitions and a coherent interconnect selectively control transition from a current power state to a new power state by each receiver partition of one or more partition groups of the plurality of partition groups.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: March 17, 2020
    Assignee: Arm Limited
    Inventors: Mark David Werkheiser, Dominic William Brown, Ashley John Crawford, Paul Gilbert Meyer
  • Publication number: 20190347217
    Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Inventors: Michael FILIPPO, Jamshed JALAL, Klas Magnus BRUCE, Paul Gilbert MEYER, David Joseph HAWKINS, Phanindra Kumar MANNAVA, Joseph Michael PUSDESRIS
  • Patent number: 10423466
    Abstract: A method, system, and device provide for the streaming of ordered requests from one or more Senders to one or more Receivers over an un-ordered interconnect while mitigating structural deadlock conditions.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: September 24, 2019
    Assignee: Arm Limited
    Inventors: Ashok Kumar Tummala, Jamshed Jalal, Paul Gilbert Meyer, Dimitrios Kaseridis
  • Patent number: 10402349
    Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: September 3, 2019
    Assignee: ARM Limited
    Inventors: Michael Filippo, Jamshed Jalal, Klas Magnus Bruce, Paul Gilbert Meyer, David Joseph Hawkins, Phanindra Kumar Mannava, Joseph Michael Pusdesris
  • Patent number: 10324858
    Abstract: Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: June 18, 2019
    Assignee: ARM Limited
    Inventors: Bruce James Mathewson, Phanindra Kumar Mannava, Matthew Lucien Evans, Paul Gilbert Meyer, Andrew Brookfield Swaine
  • Publication number: 20180357178
    Abstract: Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.
    Type: Application
    Filed: June 12, 2017
    Publication date: December 13, 2018
    Inventors: Bruce James MATHEWSON, Phanindra Kumar MANNAVA, Matthew Lucien EVANS, Paul Gilbert MEYER, Andrew Brookfield SWAINE
  • Patent number: 10095631
    Abstract: A system and method for accessing on-chip and off-chip memory in an integrated circuit data processing system. The system includes a number of nodes connected by an interconnect and also includes system address map logic in which a node register table is accessed using a hash function of the memory address to be accessed. A node identifier stored in a register of the node register table is an identifier of a remote-connection node when the memory address is in off-chip memory addresses and an identifier of a local-connection node when the memory address is in the off-chip memory. Transaction requests are routed using the node identifier selected using the hash function.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 9, 2018
    Assignee: Arm Limited
    Inventors: Paul Gilbert Meyer, Gurunath Ramagiri
  • Publication number: 20180225232
    Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 9, 2018
    Inventors: Michael FILIPPO, Jamshed JALAL, Klas Magnus BRUCE, Paul Gilbert MEYER, David Joseph HAWKINS, Phanindra Kumar MANNAVA, Joseph Michael PUSDESRIS
  • Publication number: 20180225216
    Abstract: Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 9, 2018
    Inventors: Michael FILIPPO, Jamshed JALAL, Klas Magnus BRUCE, Alex James WAUGH, Geoffray LACOURBA, Paul Gilbert MEYER, Bruce James MATHEWSON, Phanindra Kumar MANNAVA
  • Publication number: 20180225214
    Abstract: Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 9, 2018
    Inventors: Phanindra Kumar MANNAVA, Bruce James MATHEWSON, Jamshed JALAL, Klas Magnus BRUCE, Michael FILIPPO, Paul Gilbert MEYER, Alex James WAUGH, Geoffray Matthieu LACOURBA
  • Patent number: 9891976
    Abstract: Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: February 13, 2018
    Assignee: ARM Limited
    Inventors: Andy Wangkun Chen, Mudit Bhargava, Paul Gilbert Meyer, Vikas Chandra
  • Patent number: 9809005
    Abstract: Anti-ballistic systems and methods for making same are described. The anti-ballistic systems may be formed from various materials arranged in a structure, such as a wall structure. For example, an anti-ballistic system may be formed from a metal material, a polymer material, and a stone material. In some embodiments, the metal material may include aluminum (for example, an aluminum composite panel), the polymer material may include ethylene vinyl acetate, and the stone material may include granite. The anti-ballistic wall systems may be configured to be resistant to ballistics, blasts, and/or forced entry.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: November 7, 2017
    Assignee: Antiballistic Security and Protection, Inc.
    Inventors: Richard Grieves, Gilbert Meyer, Leif Lundkvist
  • Publication number: 20170168876
    Abstract: A method, system, and device provide for the streaming of ordered requests from one or more Senders to one or more Receivers over an un-ordered interconnect while mitigating structural deadlock conditions.
    Type: Application
    Filed: October 18, 2016
    Publication date: June 15, 2017
    Applicant: ARM Limited
    Inventors: Ashok Kumar TUMMALA, Jamshed JALAL, Paul Gilbert MEYER, Dimitrios KASERIDIS