Abstract: The synchronous serial bus between a main processing unit and a peripheral unit includes a data line and a clock line. Strobe pulses presented by the main processing unit on the data line while it holds the clock line at a given logic level characterise transfer cycles on the bus. The main processing unit can thus run write or read cycles in registers of an interface of the peripheral unit. A direct transfer mode, wherein the strobe pulse is transmitted at the beginning of the cycle without specifying an address, is provided to enable the main processing unit to have a fast access to certain locations previously specified. The data and clock lines of the bus may be shared with those of another synchronous bus.