Abstract: A computer-implemented method for compensation of errors due to fabrication tolerance in an analog neural network is described. The method includes: receiving a set of input weights from a trained digital neural network, the digital neural network having the same architecture as the analog neural network and being trained in a digital environment without errors due to fabrication tolerance; loading the set of input weights to the analog neural network; receiving (i) a set of test inputs for error compensation, and (ii) a set of expected outputs that is obtained by processing the set of test inputs using the trained digital neural network; processing the set of test inputs using the analog neural network to generate a set of test outputs; processing the set of test outputs and the set of expected outputs to generate a set of updated weights for the analog neural network; and loading the set of updated weights to the analog neural network.

Abstract: An apparatus includes an analog neural network, a digital controller and a memory device. The analog neural network can include a first layer having a plurality of neurons. The plurality of neurons can be reused to form a second layer of the analog neural network. Each neuron can have a plurality of inputs. The digital controller can be coupled to the analog neural network, and can provide a weight for each input of the plurality of inputs. The memory device can be coupled to the digital controller to store the weight for each input of the plurality of inputs.

Abstract: A system including a multi-layer analog neural network that has a single layer of physical analog neurons that is re-usable for implementing a plurality of layers of the multi-layer analog neural network. Each of the physical analog neurons is configured to receive a neuron input and to process the neuron input to generate a neuron output that is fed as input to all physical analog neurons of the single layer, and each of the physical analog neurons includes a respective weight memory. The system controller is operable to obtain, for each physical analog neuron, a respective set of neuron weight vectors with each neuron weight vector corresponding to a respective layer of the plurality of layers of the multi-layer analog neural network; store, for each physical analog neuron, the respective set of neuron weights in the respective weight memory of the physical analog neuron.

Abstract: Driving circuit comprises a first input, at which a first supply voltage is present, a second input, at which a second supply voltage is present, a first current supply unit selectively coupled to first or second input as function of at least one first control signal, at least one second current supply unit selectively coupled to first or second input as function of at least one second control signal, a control unit connected to first current supply unit and to at least one second current supply unit for respective control thereof and designed to provide at least one first and second control signal, and a first output coupled to first current supply unit to provide a first current for at least one first light-emitting diode, at least one second output coupled to at least one second current supply unit to provide second current for at least one second light-emitting diode.

Abstract: In one embodiment, the current source arrangement comprises a current source (B), that has two output terminals (102, 103) and a control input (101) to be supplied with a control voltage (Vgs) and is set up to provide a current (I) as a function of a voltage (Vds) at the output terminals (102, 103) and the control voltage (Vgs), an operating point adjustment unit (E) that is supplied with an actual value (Vi) proportional to an actual value of the current (I) and is set up to provide the control voltage (Vgs) as a function of the actual value (Vi) and a predetermined target value (Iz) of the current (I), and a comparison unit (A) coupled to the control input (101) of the current source (B) for providing a monitoring signal (100), wherein the monitoring signal (100) is provided as a function of a predetermined limit voltage (VG) and the control voltage (Vgs). A method for operating a current source arrangement is also specified.

Abstract: Driving circuit comprises a first input, at which a first supply voltage is present, a second input, at which a second supply voltage is present, a first current supply unit selectively coupled to first or second input as function of at least one first control signal, at least one second current supply unit selectively coupled to first or second input as function of at least one second control signal, a control unit connected to first current supply unit and to at least one second current supply unit for respective control thereof and designed to provide at least one first and second control signal, and a first output coupled to first current supply unit to provide a first current for at least one first light-emitting diode, at least one second output coupled to at least one second current supply unit to provide second current for at least one second light-emitting diode.

Abstract: In one embodiment, the current source arrangement comprises a current source (B), that has two output terminals (102, 103) and a control input (101) to be supplied with a control voltage (Vgs) and is set up to provide a current (I) as a function of a voltage (Vds) at the output terminals (102, 103) and the control voltage (Vgs), an operating point adjustment unit (E) that is supplied with an actual value (Vi) proportional to an actual value of the current (I) and is set up to provide the control voltage (Vgs) as a function of the actual value (Vi) and a predetermined target value (Iz) of the current (I), and a comparison unit (A) coupled to the control input (101) of the current source (B) for providing a monitoring signal (100), wherein the monitoring signal (100) is provided as a function of a predetermined limit voltage (VG) and the control voltage (Vgs). A method for operating a current source arrangement is also specified.

Abstract: An analogue/digital converter arrangement and a method. A differential input voltage is converted by means of a differentially implemented capacitative voltage divider that comprises two programmable capacitor banks (3, 4), and with the aid of the comparator (6) into a digital output signal.

Abstract: An analogue/digital converter arrangement and a method. A differential input voltage is converted by means of a differentially implemented capacitative voltage divider that comprises two programmable capacitor banks (3, 4), and with the aid of the comparator (6) into a digital output signal.