Abstract: A computer system couples multiple function units using channels having full-duplex, low power, point-to-point interconnect. Each function unit couples to the channel via a Channel Interface Block (CIB). The CIB includes a transmitter and a receiver. The receiver includes an integrating sampling capacitor, pass-gates having particular resistive characteristics, an auto-zero inverter, and a set of inverter stages for squaring the output of the inverter. These components are used to implement sampled-data methods and structures that perform received data extraction from the full-duplex channel signal.

Abstract: An apparatus and method for synchronizing and tracking an input data stream and for generating a synchronous clock therefrom, comprising means for generating a plurality of clock signals oscillating at substantially the same frequency, but with different phases; a plurality of delay lines having a common data input for receiving said input data stream, each delay line having multiple delay elements connected in series and having a common clock input for receiving one of said clock signals for clocking data of said data stream along said delay line in a direction away from said common data input; means for detecting which of said plurality of delay lines said data from said data stream is propagating therein; and means for generating the synchronous clock based on one of said clock signals that clocks the delay line that data from said data stream is propagating therein.

Abstract: An apparatus and method for synchronizing and tracking an input data stream and for generating a synchronous clock therefrom, comprising means for generating a plurality of clock signals oscillating at substantially the same frequency, but with different phases; a plurality of delay lines having a common data input for receiving said input data stream, each delay line having multiple delay elements connected in series and having a common clock input for receiving one of said clock signals for clocking data of said data stream along said delay line in a direction away from said common data input; means for detecting which of said plurality of delay lines said data from said data stream is propagating therein; and means for generating the synchronous clock based on one of said clock signals that clocks the delay line that data from said data stream is propagating therein.

Abstract: A phase-locked loop implemented in all-digital components uses a stochastic approach to detect errors in phase position and relative velocity. Using a history circuit and an adjustment-intensity selection circuit appropriate corrections in phase and frequency are made. The history circuit keeps a running record of a series of binary results (0 or 1) as received from a phase comparator. History components collected include the number of consecutive oscillator periods in which the phase offset (0 or 1) has remained the same and the number of oscillator periods in which the phase offset count has not exceeded 1.

Abstract: This disclosure concerns digital correction of oscillator drift by providing phase alignment between two clock signals running at nearly the same frequency. Phase alignment is provided by fashioning a delay for one of the clock signals through selection of various lengths of a variable delay path formed from a series of logic circuits. Respective reference signals are derived from the two clocks to be phase-aligned, and the phases of the references are compared in a digital phase comparator. The product of phase comparison controls a digital delay selector to generate a sequence of delay signals corresponding to a sequence of detected phase differences. The delay signal sequence controls the variable digital delay. The variable digital delay outputs a corrected clock signal whose phase is aligned with the phase of the other clock signals. The corrected clock signal is used to produce one reference signal, the other reference signal being derived directly from the other clock signal.