Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Abstract: The velocity of a wireless communications device (WCD) is estimated. In response to this estimated velocity, a tracking speed of a filter is determined that corresponds to the estimated velocity. The filter filters a timing error signal to produce a control signal that controls the timing of a synchronization clock. This synchronization clock may be a finger clock that controls the timing of a pseudonoise (PN) sequence generator configured for despreading a pilot symbol sequence.

Abstract: A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions may, but are not required to, occur across memory word boundaries. Preferably, the variable length instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation (or operations) to be performed, thereby allowing multiple operations to be performed during each clock cycle. This reduces the total number of clock cycles necessary to perform a task.

Abstract: A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

Abstract: DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.

Abstract: The velocity of a wireless communications device (106) is estimated. In response to this estimate, a filter bandwidth, such as a pilot filter (310) bandwidth, is adjusted so that the introduction of noise and distortion to a signal received by the device is mitigated. The filter bandwidth is adjusted by increasing it as the estimated velocity increases; and decreasing it as the estimated velocity decreases. Such adjustments may be accomplished through providing a number of predetermined bandwidths that each correspond to a particular velocity range, and setting the filter bandwidth to the predetermined bandwidth that corresponds to the estimated velocity.

Abstract: The velocity of a wireless communications device (WCD) is estimated. In response to this estimated velocity, a tracking speed of a filter is determined that corresponds to the estimated velocity. The filter filters a timing error signal to produce a control signal that controls the timing of a synchronization clock. This synchronization clock may be a finger clock that controls the timing of a pseudonoise (PN) sequence generator configured for despreading a pilot symbol sequence.