Abstract: Techniques for an extended prefix including a routing bit for an extended instruction format are described herein. An aspect includes generating, by an instruction preprocessing module, a first extended instruction corresponding to an internal operation including a first routing bit. Another aspect includes generating, by the instruction preprocessing module, a second extended instruction corresponding to a prefixed instruction set architecture (ISA) instruction including a second routing bit, wherein a value of the second routing bit is opposite a value of the first routing bit. Another aspect includes providing the first extended instruction and the second extended instruction to a central processing unit (CPU). Another aspect includes, based on the value of the first routing bit, routing the internal operation directly to an execution unit of the CPU, and based on the value of the second routing bit, routing the prefixed ISA instruction to a decode/execute path of the CPU.

Abstract: A dual outcome event monitoring unit comprises a plurality of inputs, and a first counter. Each input is associated with an event and the first counter is a bidirectional counter. The dual outcome event monitoring unit is configured to increment the first counter in response to receiving an indication of the occurrence of a first event of a plurality of events. The first event is designated as an increment event. The dual outcome event monitoring unit is also configured to decrement the first counter responsive to receiving an indication of the occurrence of a second event of a plurality of events. The second event is designated as a decrement event.

Abstract: An indication that an event occurred is received from a processor by a dual outcome event monitoring unit. It is determined whether the event is associated with an increment event or a decrement event. In response to determining that the event is associated with the increment event, an event counter is incremented. The event counter is part of the dual outcome monitoring unit. In response to determining that the event is associated with the decrement event, the event counter is decremented.

Abstract: Methods, systems, and computer program products are provided for migrating an operating system from a source computer to a destination computer. Some embodiments include identifying a destination adapter of the destination computer that is coupled for data communications to a SAN that is also coupled for data communications to a source adapter of the source computer, logging off a virtual port name of the source adapter from the login manager, deregistering the virtual port name from the source adapter, registering the virtual port name with the destination adapter, and logging on the destination adapter to the login manager with the virtual port name. Typical embodiments also include transferring the operating system from the source computer to the destination computer.

Abstract: A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one or more register values accessible by the first hardware thread. Next, the first hardware thread copies the identified register values to one or more registers accessible by the second hardware thread. In turn, the second hardware thread accesses the copied register values included in the accessible registers and executes software code accordingly.

Abstract: A dual outcome event monitoring unit comprises a plurality of inputs, and a first counter. Each input is associated with an event and the first counter is a bidirectional counter. The dual outcome event monitoring unit is configured to increment the first counter in response to receiving an indication of the occurrence of a first event of a plurality of events. The first event is designated as an increment event. The dual outcome event monitoring unit is also configured to decrement the first counter responsive to receiving an indication of the occurrence of a second event of a plurality of events. The second event is designated as a decrement event.

Abstract: An indication that an event occurred is received from a processor by a dual outcome event monitoring unit. It is determined whether the event is associated with an increment event or a decrement event. In response to determining that the event is associated with the increment event, an event counter is incremented. The event counter is part of the dual outcome monitoring unit. In response to determining that the event is associated with the decrement event, the event counter is decremented.

Abstract: A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one or more register values accessible by the first hardware thread. Next, the first hardware thread copies the identified register values to one or more registers accessible by the second hardware thread. In turn, the second hardware thread accesses the copied register values included in the accessible registers and executes software code accordingly.

Abstract: A processor recognizes a request from a program executing on a first hardware thread to initiate software code on a second hardware thread. In response, the second hardware thread initiates and commences executing the software code. During execution, the software code uses hardware registers of the second hardware thread to store data. Upon termination of the software code, the second hardware thread invokes a hypervisor program, which extracts data from the hardware registers and stores the extracted data in a shared memory area. In turn, a debug routine executes and retrieves the extracted data from the shared memory area.

Abstract: A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating.

Abstract: A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating.

Abstract: A processor recognizes a request from a program executing on a first hardware thread to initiate software code on a second hardware thread. In response, the second hardware thread initiates and commences executing the software code. During execution, the software code uses hardware registers of the second hardware thread to store data. Upon termination of the software code, the second hardware thread invokes a hypervisor program, which extracts data from the hardware registers and stores the extracted data in a shared memory area. In turn, a debug routine executes and retrieves the extracted data from the shared memory area.

Abstract: A processor recognizes a request from a program executing on a first hardware thread to initiate software code on a second hardware thread. In response, the second hardware thread initiates and commences executing the software code. During execution, the software code uses hardware registers of the second hardware thread to store data. Upon termination of the software code, the second hardware thread invokes a hypervisor program, which extracts data from the hardware registers and stores the extracted data in a shared memory area. In turn, a debug routine executes and retrieves the extracted data from the shared memory area.

Abstract: A processor recognizes a request from a program executing on a first hardware thread to initiate software code on a second hardware thread. In response, the second hardware thread initiates and commences executing the software code. During execution, the software code uses hardware registers of the second hardware thread to store data. Upon termination of the software code, the second hardware thread invokes a hypervisor program, which extracts data from the hardware registers and stores the extracted data in a shared memory area. In turn, a debug routine executes and retrieves the extracted data from the shared memory area.

Abstract: A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one or more register values accessible by the first hardware thread. Next, the first hardware thread copies the identified register values to one or more registers accessible by the second hardware thread. In turn, the second hardware thread accesses the copied register values included in the accessible registers and executes software code accordingly.

Abstract: A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating.

Abstract: A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one or more register values accessible by the first hardware thread. Next, the first hardware thread copies the identified register values to one or more registers accessible by the second hardware thread. In turn, the second hardware thread accesses the copied register values included in the accessible registers and executes software code accordingly.

Abstract: The present invention relates to a method, a computer program product and a system for managing virtual instances of a physical port attached to a network. The method is based on the Fiber Channel N_Port virtualisation for a physical Fibre Channel N_Port. Multiple virtual Fibre Channel adapters share a single physical N_Port among multiple operating system instances. The invention discloses means for the automatic and persistent generation and administration of unique Worldwide Port Names needed for the N_Port virtualisation.

Abstract: A computer-implemented method, apparatus, and computer-usable program code to generate unique identifiers for a logically partitioned and/or virtualized data processing system. A number of computing entities supported by the data processing system are identified to form a number of identified entities. A set of unique identifiers is generated based upon the number of identified entities. A unique identifier from the set of unique identifiers is assigned to a logical computing entity during operation of the data processing system.

Abstract: Systems and arrangements to adjust resource accessibility based upon usage modes are contemplated. Embodiments may include a supervisor instance such as an operating system that is adapted to select one or more supervisor keys from a set of supervisor keys available to the host node or platform upon which the supervisor instance is operating. The supervisor instance may select the supervisor key(s) based upon an association of the supervisor instance with a usage mode represented by a supervisor key name. In many embodiments, supervisor key names may be associated with resources via with one or more of the supervisor keys based upon the resources needed when operating in the usage modes by a system administrator. Once the supervisor instance is initialized, the supervisor instance may issue client keys that allow access to subsets of the resources available to the supervisor instance based upon usage modes of the clients.