Abstract: Processing methods may be performed to form semiconductor structures that may include three-dimensional memory structures. The methods may include forming a plasma of a fluorine-containing precursor in a remote plasma region of a processing chamber. The methods may include contacting a semiconductor substrate with effluents of the plasma. The semiconductor substrate may be housed in a processing region of the processing chamber. The methods may include selectively cleaning exposed nitride materials with the effluents of the plasma. The methods may also include subsequently depositing a cap material over the cleaned nitride material. The cap material may be selectively deposited on the nitride material relative to exposed regions of a dielectric material.

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming, on a substrate, a stack of alternating layers including a first layer of material and a second layer of material different from the first layer of material; forming a memory hole in the stack of alternating layers of the first layer of material and the second layer of material; depositing a layer of blocking oxide on sides defining the memory hole; depositing a layer of silicon atop the layer of blocking oxide to form a silicon channel; deposit core oxide to fill the silicon channel; removing the first layer of material to form spaces between the alternating layers of the second material; and one of depositing a third layer of material to partially fill the spaces to leave air gaps therein or depositing a fourth layer of material to fill the spaces.

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming, on a substrate, a stack of alternating layers including a first layer of material and a second layer of material different from the first layer of material; forming a memory hole in the stack of alternating layers of the first layer of material and the second layer of material; depositing a layer of blocking oxide on sides defining the memory hole; depositing a layer of silicon atop the layer of blocking oxide to form a silicon channel; deposit core oxide to fill the silicon channel; removing the first layer of material to form spaces between the alternating layers of the second material; and one of depositing a third layer of material to partially fill the spaces to leave air gaps therein or depositing a fourth layer of material to fill the spaces.

Abstract: Processing methods may be performed to form semiconductor structures that may include three-dimensional memory structures. The methods may include forming a plasma of a fluorine-containing precursor in a remote plasma region of a processing chamber. The methods may include contacting a semiconductor substrate with effluents of the plasma. The semiconductor substrate may be housed in a processing region of the processing chamber. The methods may include selectively cleaning exposed nitride materials with the effluents of the plasma. The methods may also include subsequently depositing a cap material over the cleaned nitride material. The cap material may be selectively deposited on the nitride material relative to exposed regions of a dielectric material.

Abstract: Methods and apparatuses for substrate fabrication are provided herein.

Abstract: A transistor cell and method of making a transistor cell is disclosed. In one embodiment a transistor cell, includes first metal line spacers and the first gate spacers that vertically at least partially overlap, wherein second metal line spacers and second gate spacers vertically at least partially overlap. A contact region is defined above a second source/drain region and/or a third source/drain region by a respective adjacent first metal line spacer and second metal line spacer and by a respective adjacent first gate spacer and second gate spacer. A contact via vertically extends from the contact region at least to the layer of the first metal line.

Abstract: Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices, wherein the second magnetic layer or free layer of a magnetic stack may be patterned using a wet etch technique. A cap layer is formed over the free layer after the free layer is patterned. The cap layer is formed using lift-off techniques. To form the cap layer, resist layers are deposited and patterned, and material layers are deposited over the resist layers. Portions of the material layers are removed when the resist is stripped.

Abstract: Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of an MTJ. The first material of the hard mask is thin and comprises an etch-resistant material. The second material of the hard mask deposited over the first material is thicker and is less etch-resistant than the first material. At least a portion of the second material is sacrificially removed during the etch process of the lower magnetic material layers. A conformal or non-conformal material may be used as the second material of the hard mask. The hard mask used to pattern lower magnetic materials of an MTJ may comprise a single layer of non-conformal material.

Abstract: A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.

Abstract: A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.