Abstract: An amplifier circuit is disclosed which receives signals that cause the amplifier to be configured in an asymmetrical mode or symmetrical mode, so that performance may be optimized in each mode.

Abstract: An output stage for an amplifier AMP includes a first transistor T1 and a second transistor T2 having their main current paths arranged between two power supply terminals VCC and GND, the bias terminal of the first transistor T1 being connected to the output of the amplifier AMP and the bias terminal of the second transistor T2 being connected to the input of the amplifier AMP via a bias circuit BC. The bias circuit includes a detection module intended to signal the instant when the second transistor T2 enters the state of saturation, and an impedance matching module intended, when activated, to attribute a high impedance to the bias terminal of the second transistor T2 when the transistor becomes saturated. The circuit limits the value of a parasitic current injected into the substrate via a parasitic transistor PT2 which appears when the second transistor T2 is saturated.

Abstract: A current amplifier A1 includes two transistors Q1 and Q2 whose emitters are interconnected via a resistor R1. The input of the current amplifier is constituted by the emitter of the first transistor Q1, whose collector is connected to the output terminal of the amplifier A1 via a second resistor R2, and to the first resistor R1 via the main current path of the second transistor Q2. The current amplifier A1 has a simple structure and a low input impedance, as well as an easily controllable gain.

Abstract: A comparator (22) compares the output signal (Vout) supplied by an output amplifier (21) with an input signal (Vin). Dependent on the result of the comparison, it controls the conduction of one or the other of two sources (IGA, IGB) which supply opposite currents. Two complementary assemblies (A, B) each comprise a first transistor (T1A, T1B) and a second transistor (T2A, T2B). Each first transistor (T1A, T1B) has its base controlled by one of the current sources for charging a first capacitance (C1) connected to the output, and also controls the conduction of the corresponding second transistor. The bases of the second transistors (T2A, T2B) are jointly connected to the first capacitance (C1) and their emitters are jointly connected to the negative input of the output amplifier (21). The negative input of the output amplifier (21) is also connected to a reference voltage (Vref) via a resistor (20) and to the output (Vout) via a second capacitance (C2).

Abstract: The circuit (7, 8, 9, 10) comprises, in addition to the automatic gain control (AGC), a gain reduction means for controlling the gain of an amplifier (8), intended to avoid the desynchronization of the local oscillator (7) controlled by a phase-locked loop comparator (12). This is controlled by a peak detector of the amplified signal situated at the output of the amplifier (8).

Abstract: Tuning circuit in which a local oscillator is constituted by an amplifier which is coupled to a resonant circuit of the variable capacitance and inductance type, the amplifier having a first stage formed by at least one differential pair of bipolar transistors (T1, T2). The amplifier has also a second stage with another differential pair of transistors whose linked emitters are fed by the collector current of one (T2) of the transistors of the first stage. A transistor (T3) of the differential pair of the second stage has its collector coupled to a main load resistor (RL) and its base coupled to the collector of the other transistor (T1) of the first stage, which feeds a supplementary load resistor (Rb). The base of the other transistor (T4) of the differential pair of the second stage may be polarized at a fixed voltage (Vref2) or at a variable voltage, having the appropriate.

Abstract: An integratable transformer circuit for converting an asymmetrical input signal into a pair of symmetrical output signal currents and requiring only one IC connection pin. The circuit exhibits a low input impedance combined with good noise, gain and intermodulation performance up to high frequencies. The asymmetrical input terminal of the circuit is coupled to a node commonly coupled to the emitter of a common base transistor and to the base of a common emitter transistor. The common base transistor acts as a non-inverting current follower, the common emitter transistor as an inverting transimpedance amplifier. An input signal current is transferred to a first symmetrical output terminal via the node and the common base transistor, thereby producing a signal voltage at the node. This signal voltage modulates the collector current of the common emitter transistor, which is in phase opposition to the input signal current and is transferred to the second output terminal.

Abstract: A differential amplifier of the cascode type comprises a differential stage which includes a first (T.sub.1) and a second (T.sub.2) transistor whose collectors are connected to an active load constituted by the respective collector-emitter paths of a third (T.sub.3) and a fourth (T.sub.4) transistor in series with a first and a second resistor, respectively. One end of each resistor is connected to a supply voltage terminal. The third and the fourth transistor have their bases connected to a reference voltage terminal. A first capacitor (C.sub.1) is coupled between the collector-emitter paths of the third and of the first transistor, and a second capacitor (C.sub.2) is arranged between the collector-emitter paths of the fourth and of the second transistor. A third (R'.sub.1) and a fourth (R'.sub.2) resistor are connected between the supply voltage terminal (V.sub.cc) and the collector-emitter path of the first transistor and of the second transistor, respectively.

Abstract: A wideband amplifier having a direct output (C) to which is connected a level shifting stage providing at least one level shifted output. A first transistor emitter follower (Q.sub.3) is arranged in series with at least one level shifting element (Q.sub.4). The first transistor (Q.sub.3) has first resistor (R.sub.2) disposed between its base and a supply voltage source (V.sub.cc). A negative feedback circuit (R.sub.F1) is coupled to at least one level shifted output. The level shifting stage also includes at least second and third transistors (Q.sub.20, Q.sub.30) whose bases are connected to one said level shifted output (S) and which are arranged so that their collectors form separate first and second outputs (S.sub.1, S.sub.2) respectively. A fourth emitter follower (Q'.sub.3) is cascaded between the first emitter follower (Q.sub.3) and the level shifting element (Q.sub.4). A fifth transistor (Q.sub.