Patents by Inventor Gilles Eric Grandou
Gilles Eric Grandou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9639484Abstract: A data processing system (2) includes memory protection circuitry (10) storing access control data for controlling accesses to data at memory addresses within a main memory (16). An access control cache (14) may, in one embodiment, store access control data when the access control data is indicated by the memory protection circuitry (10) to be cachable. In another embodiment access control data is stored within the access control cache with determined address range data for reach determination of access control data by the memory protection circuitry. If the access control cache (14) is storing access control data for a memory access request, then the access control data stored within the access control cache (14) is used in place of access control data retrieved form the memory protection circuitry (10).Type: GrantFiled: September 27, 2011Date of Patent: May 2, 2017Assignee: ARM LimitedInventors: Simon John Craske, Melanie Emanuelle Lucie Teyssier, Nicolas Jean Phillippe Huot, Gilles Eric Grandou
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Patent number: 9442856Abstract: A data processing apparatus has data processing circuitry for performing data processing operations on data, and a hierarchical cache structure for storing at least a subset of the data for access by the data processing circuitry. The hierarchical cache structure has first and second level caches, and data evicted from the first level cache is routed to the second level cache under the control of second level cache access control circuitry. Cache maintenance circuitry performs a cache maintenance operation in both the first level cache and the second level cache. The access control circuitry is responsive to maintenance indication data to modify the eviction handling operation performed in response to the evicted data, so as to cause the required cache maintenance for the second level cache to be incorporated within the eviction handling operation.Type: GrantFiled: June 5, 2015Date of Patent: September 13, 2016Assignee: ARM LimitedInventors: Gilles Eric Grandou, Philippe Jean-Pierre Raphalen, Andrea Mascheroni
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Publication number: 20150269079Abstract: A data processing apparatus has data processing circuitry for performing data processing operations on data, and a hierarchical cache structure for storing at least a subset of the data for access by the data processing circuitry. The hierarchical cache structure has first and second level caches, and data evicted from the first level cache is routed to the second level cache under the control of second level cache access control circuitry. Cache maintenance circuitry performs a cache maintenance operation in both the first level cache and the second level cache. The access control circuitry is responsive to maintenance indication data to modify the eviction handling operation performed in response to the evicted data, so as to cause the required cache maintenance for the second level cache to be incorporated within the eviction handling operation.Type: ApplicationFiled: June 5, 2015Publication date: September 24, 2015Inventors: Gilles Eric GRANDOU, Philippe Jean-Pierre RAPHALEN, Andrea MASCHERONI
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Patent number: 9081685Abstract: A data processing apparatus has data processing circuitry for performing data processing operations on data, and a hierarchical cache structure for storing at least a subset of the data for access by the data processing circuitry. The hierarchical cache structure has first and second level caches, and data evicted from the first level cache is routed to the second level cache under the control of second level cache access control circuitry. Cache maintenance circuitry performs a cache maintenance operation in both the first level cache and the second level cache. The access control circuitry is responsive to maintenance indication data to modify the eviction handling operation performed in response to the evicted data, so as to cause the required cache maintenance for the second level cache to be incorporated within the eviction handling operation.Type: GrantFiled: January 15, 2013Date of Patent: July 14, 2015Assignee: ARM LimitedInventors: Gilles Eric Grandou, Philippe Jean-Pierre Raphalen, Andrea Mascheroni
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Publication number: 20140201447Abstract: A data processing apparatus has data processing circuitry for performing data processing operations on data, and a hierarchical cache structure for storing at least a subset of the data for access by the data processing circuitry. The hierarchical cache structure has first and second level caches, and data evicted from the first level cache is routed to the second level cache under the control of second level cache access control circuitry. Cache maintenance circuitry performs a cache maintenance operation in both the first level cache and the second level cache. The access control circuitry is responsive to maintenance indication data to modify the eviction handling operation performed in response to the evicted data, so as to cause the required cache maintenance for the second level cache to be incorporated within the eviction handling operation.Type: ApplicationFiled: January 15, 2013Publication date: July 17, 2014Applicant: ARM LIMITEDInventors: Gilles Eric GRANDOU, Philippe Jean-Pierre RAPHALEN, Andrea MASCHERONI
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Publication number: 20130290635Abstract: A data processing system (2) includes memory protection circuitry (10) storing access control data for controlling accesses to data at memory addresses within a main memory (16). An access control cache (14) may, in one embodiment, store access control data when the access control data is indicated by the memory protection circuitry (10) to be cachable. In another embodiment access control data is stored within the access control cache with determined address range data for reach determination of access control data by the memory protection circuitry. If the access control cache (14) is storing access control data for a memory access request, then the access control data stored within the access control cache (14) is used in place of access control data retrieved form the memory protection circuitry (10).Type: ApplicationFiled: September 27, 2011Publication date: October 31, 2013Applicant: ARM LIMITEDInventors: Simon John Craske, Melanie Emanuelle Lucie Teyssier, Nicolas Jean Phillippe Huot, Gilles Eric Grandou
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Patent number: 8151055Abstract: A data processing apparatus includes a data processor, and a data store for storing a plurality of identifiers identifying a cache way in which a corresponding value from a set associative cache is stored. The plurality of identifiers corresponding to a plurality of values stored in consecutive addresses such that a data store stores identifiers for values stored in a region of said memory. Included is a current pointer store for pointing to a most recently accessed storage location in said data store and circuitry to determine an offset of an address of said cache access request to an immediately preceding cache access request. Lookup circuitry determines if said pointer is pointing to an address within said region and said data processor identifies said cache way from said stored identifier pointed to by said current pointer if it has a valid indicator associated therewith.Type: GrantFiled: February 25, 2009Date of Patent: April 3, 2012Assignee: ARM LimitedInventors: Louis-Marie Vincent Mouton, Nicolas Jean Phillippe Huot, Gilles Eric Grandou, Stephane Eric Sebastian Brochier
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Patent number: 7925871Abstract: A data processing apparatus 2 is provided with one or more branch predictors 10 for generating branch predictions. A supervising predictor 12 is responsive to at least a stream of branch predictions to identify one or more cyclically recurring errors in the branch predictors and generate corrected behaviours for a prefetch unit 4.Type: GrantFiled: February 19, 2008Date of Patent: April 12, 2011Assignee: ARM LimitedInventors: Louis Marie Vincent Mouton, Nicolas Huot, Stephane Eric Sebastien Brochier, Gilles Eric Grandou
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Patent number: 7917701Abstract: Prefetch circuitry is provided which is responsive to a determination that the memory address of a data value specified by a current access request is the same as a predicted memory address, to perform either a first prefetch linefill operation or a second prefetch linefill operation to retrieve from memory at least one further data value in anticipation of that data value being the subject of a subsequent access request. The selection of either the first prefetch linefill operation or the second prefetch linefill operation is performed in dependence on an attribute of the current access request.Type: GrantFiled: March 12, 2007Date of Patent: March 29, 2011Assignee: ARM LimitedInventors: Elodie Charra, Philippe Jean-Pierre Raphalen, Frederic Claude Marie Piry, Philippe Luc, Gilles Eric Grandou
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Patent number: 7797520Abstract: A data processing apparatus including a prefetch unit for prefetching the instructions from a memory, branch prediction logic and a branch target cache for storing predetermined information about branch operations executed by the processor. The information includes identification of an instruction specifying a branch operation, a target address for said branch operation and a prediction as to whether said branch operation is taken or not. The prefetch unit accesses said branch target cache at least one clock cycle prior to fetching an instruction from said memory, to determine if there is predetermined information corresponding to said instruction stored within said branch target cache.Type: GrantFiled: June 30, 2005Date of Patent: September 14, 2010Assignee: ARM LimitedInventors: Gilles Eric Grandou, Phillippe Jean-Pierre Raphalen, Richard Roy Grisenthwaite
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Patent number: 7783869Abstract: A data processing apparatus is disclosed that comprises: a processor for processing a stream of decoded instructions; a prefetch unit for fetching instructions within a stream of instructions from a memory prior to sending said stream of instructions to said processor; branch prediction logic operable to predict a behaviour of a branch instruction; a branch target cache for storing predetermined information about branch operations executed by said processor, said predetermined information comprising: identification data for an instruction specifying a branch operation and data relating to whether said branch is taken or not; wherein said data processing apparatus is operable to access said branch target cache and to determine if there is data corresponding to instructions within said stream of instructions stored within said branch target cache and if there is to output said data; said data processing apparatus further comprising: a data store operable to store data indicative of a behaviour of a branch instrType: GrantFiled: December 19, 2006Date of Patent: August 24, 2010Assignee: ARM LimitedInventors: Gilles Eric Grandou, Stephane Eric Sebastien Brochier, Louis-Marie Vincent Mouton
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Patent number: 7761665Abstract: The present invention provides a data processing apparatus and method for handling cache accesses. The data processing apparatus comprises a processing unit operable to issue a series of access requests, each access request having associated therewith an address of a data value to be accessed. Further, the data processing apparatus has an n-way set associative cache memory operable to store data values for access by the processing unit, each way of the cache memory comprising a plurality of cache lines, and each cache line being operable to store a plurality of data values. The cache memory further comprises for each way a TAG storage for storing, for each cache line of that way, a corresponding TAG value.Type: GrantFiled: May 23, 2005Date of Patent: July 20, 2010Assignee: ARM LimitedInventors: Gilles Eric Grandou, Philippe Jean-Pierre Raphalen
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Patent number: 7596663Abstract: A data processor operable to process data said data processor comprising: a set associative cache divided into a plurality of cache ways and operable to store data processed by said data processor; a buffer operable to store a table comprising a plurality of mappings of pages of virtual addresses to pages of physical addresses for said data processor; a data store comprising a plurality of data entries each operable to store data for identifying an address of a memory location for each of a plurality of recent cache accesses, each of said plurality of data entries comprising a page index indicating a page in an address space, offset data indicating a location within said page and cache way data identifying a cache way of a cache storage location accessed by said cache access; wherein said data processor is operable in response to a cache access request comprising a virtual address indicating a memory location to access said table and said data store to determine whether said cache access request is to one ofType: GrantFiled: November 15, 2006Date of Patent: September 29, 2009Assignee: ARM LimitedInventors: Louis-Marie Vincent Mouton, Gilles Eric Grandou, Stephane Eric Brochier
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Publication number: 20090235029Abstract: A data processing apparatus is disclosed that comprises: at least one data processor for processing data; a set associative cache for storing a plurality of values to be processed by said data processor, each value being identified by an address of a memory location within a memory storing said value, said set associative cache being divided into a plurality of cache ways; a data store comprising a plurality of storage locations for storing a plurality of identifiers, each identifier identifying a cache way that a corresponding value from said set associative cache is stored in and each having a valid indicator associated therewith, said plurality of identifiers corresponding to a plurality of values, said plurality of values being values stored in consecutive addresses such that said data store stores identifiers for values stored in a region of said memory; current pointer store for storing a current pointer pointing to a most recently accessed storage location in said data store; offset determining circuitType: ApplicationFiled: February 25, 2009Publication date: September 17, 2009Applicant: ARM LIMITEDInventors: Louis-Marie Vincent Mouton, Nicolas Jean Phillippe Huot, Gilles Eric Grandou, Stephane Eric Sebastian Brochier
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Patent number: 7587556Abstract: A store buffer, method and data processing apparatus is disclosed. The store buffer comprises: reception logic operable to receive a request to write a data value to an address in memory; buffer logic having a plurality of entries, each entry being selectively operable to store request information indicative of a previous request and to maintain associated cache information indicating whether a cache line in a cache is currently allocated for writing data values to an address associated with that request; and entry selection logic operable to determine which one of the plurality entries to allocate to store the request using the request information and the associated cache information of the plurality of entries to determine whether a cache line in the cache is currently allocated for writing the data value to the address in memory.Type: GrantFiled: March 29, 2006Date of Patent: September 8, 2009Assignee: ARM LimitedInventors: Frederic Claude Piry, Philippe Jean-Pierre Raphalen, Florent Begon, Gilles Eric Grandou
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Publication number: 20090210685Abstract: A data processing apparatus 2 is provided with one or more branch predictors 10 for generating branch predictions. A supervising predictor 12 is responsive to at least a stream of branch predictions to identify one or more cyclically recurring errors in the branch predictors and generate corrected behaviours for a prefetch unit 4.Type: ApplicationFiled: February 19, 2008Publication date: August 20, 2009Applicant: ARM LimitedInventors: Louis-Marie Vincent Mouton, Nicolas Huot, Stephane Eric Sebastien Brochier, Gilles Eric Grandou
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Patent number: 7571305Abstract: A data processing system 2 includes an instruction cache 6 having an associated buffer memory 18, 8. The buffer memory 18, 8 can operate in a buffer mode or in a microcache mode. The buffer memory is switched into the microcache mode upon program loop detection performed by loop detector circuitry 20. When operating in the microcache mode, instruction data is read from the buffer memory 18, 8 without requiring an access to the instruction cache 6.Type: GrantFiled: January 11, 2007Date of Patent: August 4, 2009Assignee: ARM LimitedInventors: Fredrick Claude Marie Piry, Louis-Marie Vincent Mouton, Stephane Eric Sabastien Brochier, Gilles Eric Grandou
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Publication number: 20080229070Abstract: Cache circuitry, a data processing apparatus including such cache circuitry, and a method for prefetching data into such cache circuitry, are provided. The cache circuitry has a cache storage comprising a plurality of cache lines for storing data values, and control circuitry which is responsive to an access racquet issued by a device of the data processing apparatus identifying a memory address of a data value to be accessed, to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage. If not, a linefill operation is initiated to retrieve the data value from memory.Type: ApplicationFiled: March 12, 2007Publication date: September 18, 2008Applicant: ARM LimitedInventors: Elodie Charra, Philippe Jean-Pierre Raphalen, Frederic Claude Marie Piry, Philippe Luc, Gilles Eric Grandou
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Publication number: 20080172547Abstract: A data processing system 2 includes an instruction cache 6 having an associated buffer memory 18, 8. The buffer memory 18, 8 can operate in a buffer mode or in a microcache mode. The buffer memory is switched into the microcache mode upon program loop detection performed by loop detector circuitry 20. When operating in the microcache mode, instruction data is read from the buffer memory 18, 8 without requiring an access to the instruction cache 6.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Applicant: ARM LimitedInventors: Frederic Claude Marie Piry, Louis-Marie Vincent Mouton, Stephane Eric Sabastien Brochier, Gilles Eric Grandou
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Publication number: 20080148022Abstract: The present application discloses register renaming circuitry for mapping registers from an architectural set of registers to registers within a physical set of registers, said architectural set of registers being registers specified by instructions within an instruction set and said physical set of registers being registers within a processor for processing instructions of said instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may generate an exception and non-exception instructions being instructions that execute in a statically determinable way, said register renaming circuitry comprising: a first data store for storing a future renaming table, said future renaming table comprising renaming values for mapping registers from said architectural set of registers to registers in said physical set of registers for instructions that are to be executed or are currently being executed by said processor; a second daType: ApplicationFiled: December 13, 2006Publication date: June 19, 2008Applicant: ARM LimitedInventors: Frederic Claude Marie Piry, Melanie Emanuelle Lucie Vincent, Florent Begon, Gilles Eric Grandou, Norbert Bernard Eugene Lataille