Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.

Abstract: An X-ray detector includes a first circuit with an NPN-type bipolar transistor and a second circuit configured to compare a voltage at a terminal of the NPN-type bipolar transistor with a reference value substantially equal to a value of the terminal voltage which would occur when the first circuit has been exposed to a threshold quantity of X-rays.

Abstract: An X-ray detector includes a first circuit with an NPN-type bipolar transistor and a second circuit configured to compare a voltage at a terminal of the NPN-type bipolar transistor with a reference value substantially equal to a value of the terminal voltage which would occur when the first circuit has been exposed to a threshold quantity of X-rays.

Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.

Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.

Abstract: Absorbed ionizing particles differentially effect first and second acquiring circuit stages configured to respectively generate first and second acquisition signals. Each acquisition signal has a characteristic that is variable as a function of an amount of absorbed ionizing particles. A measuring circuit generates, on the basis of the first and second acquisition signals, a relative parameter indicative of a relationship between the variable characteristics. A computation of a total ionizing dose is made using a 1st- or 2nd-degree polynomial relationship in the relative parameter.

Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.

Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.

Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.

Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.

Abstract: Absorbed ionizing particles differentially effect first and second acquiring circuit stages configured to respectively generate first and second acquisition signals. Each acquisition signal has a characteristic that is variable as a function of an amount of absorbed ionizing particles. A measuring circuit generates, on the basis of the first and second acquisition signals, a relative parameter indicative of a relationship between the variable characteristics. A computation of a total ionizing dose is made using a 1st- or 2nd-degree polynomial relationship in the relative parameter.

Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.

Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.

Abstract: A storage element including two CMOS inverters, coupled head-to-tail between two nodes; and one MOS transistor, connected as a capacitor between said nodes.

Abstract: A radiation-hardened logic device includes a first n-channel transistor coupled by its main conducting nodes between an output node of a logic device and a supply voltage rail and a first p-channel transistor coupled by its main conducting nodes between the output node of the logic device and a ground voltage rail. The gates of the first n-channel and p-channel transistors are coupled to the output node.

Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.

Abstract: A circuit including a data storage element; first and second input circuitry coupled respectively to first and second inputs of the data storage element and each including a plurality of components adapted to generate, as a function of an initial signal, first and second input signals respectively provided to the first and second inputs; wherein the data storage element includes a first storage node and is configured such that a voltage state stored at the first storage node is protected from a change in only one of the first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on the first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on the second input signal.

Abstract: A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor.

Abstract: The present invention relates to an integrated electronic circuit including elements enabling to implement a logic function and means for attenuating the sensitivity of said elements to external disturbances, said attenuation means being disconnectable during phases of intentional modification of the state of said elements.

Abstract: The present invention relates to an integrated electronic circuit including elements enabling to implement a logic function and means for attenuating the sensitivity of said elements to external disturbances, said attenuation means being disconnectable during phases of intentional modification of the state of said elements.