Patents by Inventor Gilles Gervais

Gilles Gervais has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8607080
    Abstract: A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Gilles Gervais, Alain Loiseau, Kirk D. Peterson, Norman J. Rohrer
  • Patent number: 8381006
    Abstract: A mechanism is provided for reducing power consumed by a multi-core processor. Responsive to a number of properly functioning processor cores being more than a required number of processor cores in a multi-core processor, the power consumption measurement module determines a number of the properly functioning processor cores to disable. The power consumption measurement module initiates an equal amount of workload to be processed by each of the properly functioning processor cores. The power consumption measurement module determines power consumed by each of the properly functioning processor cores. The power consumption measurement module deactivates one or more of the properly functioning processor cores that have maximum power in order that the number of properly functioning processor cores deactivated is equal to the number of properly functioning processor cores to disable.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brian K. Flachs, Gilles Gervais, Sang H. Dhong, Tetsuji Tamura
  • Patent number: 8341434
    Abstract: A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Gilles Gervais, Alain Loiseau, Kirk D. Peterson, Norman J. Rohrer
  • Publication number: 20120159203
    Abstract: A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.
    Type: Application
    Filed: February 17, 2012
    Publication date: June 21, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gilles Gervais, Alain Loiseau, Kirk D. Peterson, Norman J. Rohrer
  • Publication number: 20110252260
    Abstract: A mechanism is provided for reducing power consumed by a multi-core processor. Responsive to a number of properly functioning processor cores being more than a required number of processor cores in a multi-core processor, the power consumption measurement module determines a number of the properly functioning processor cores to disable. The power consumption measurement module initiates an equal amount of workload to be processed by each of the properly functioning processor cores. The power consumption measurement module determines power consumed by each of the properly functioning processor cores. The power consumption measurement module deactivates one or more of the properly functioning processor cores that have maximum power in order that the number of properly functioning processor cores deactivated is equal to the number of properly functioning processor cores to disable.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 13, 2011
    Applicant: International Business Machines Corporation
    Inventors: Brian K. Flachs, Gilles Gervais, Sang H. Dhong, Tetsuji Tamura
  • Patent number: 7917347
    Abstract: Mechanisms for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventors: Makoto Aikawa, Jonathan J. DeMent, Sang H. Dhong, Brian K. Flachs, Gilles Gervais, Iwao Takiguchi, Tetsuji Tamura
  • Patent number: 7890782
    Abstract: Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamiclock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: February 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Christopher Michael Abernathy, Gilles Gervais, Rolf Hilgendorf
  • Patent number: 7739573
    Abstract: A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jonathan J. DeMent, Sang H. Dhong, Gilles Gervais, Alain Loiseau, Kirk D. Peterson, John L. Sinchak
  • Patent number: 7716516
    Abstract: A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: May 11, 2010
    Assignees: Sony Computer Entertainment Inc., International Business Machines Corporation, Toshiba America Electronic Components, Inc.
    Inventors: Yosuke Muraki, Tetsuji Tamura, Iwao Takiguchi, Makoto Aikawa, Eskinder Hailu, Byron Lee Krauter, Stephen Douglas Weitzel, Jieming Qi, Kazuhiko Miki, David William Boerstler, Gilles Gervais, Kirk David Peterson, Robert Walter Berry, Jr., Sang Hoo Dhong
  • Patent number: 7610531
    Abstract: Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e.g., an on-chip voltage, which approximates a nominal circuit voltage, such as produced by the application of other portions of the sequence of states in the same or different test sequences. For example, hold state cycles or shift-scan state cycles may be inserted or removed prior to test state cycles in the test pattern waveform. The insertion/removal shifts the occurrence of the test state cycles within the test pattern waveform so as to adjust the voltage response of the test state cycles so that they more closely approximate a nominal voltage response. In this way, false failures due to noise in the voltage supply may be eliminated.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: October 27, 2009
    Assignee: International Business Machines Corporation
    Inventors: Sang H. Dhong, Brian Flachs, Gilles Gervais, Brad W. Michael, Mack W. Riley
  • Publication number: 20090217059
    Abstract: A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 27, 2009
    Inventors: Gilles Gervais, Alain Loiseau, Kirk D. Peterson, Norman J. Rohrer
  • Publication number: 20090112550
    Abstract: A system and method for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 30, 2009
    Inventors: Makoto Aikawa, Jonathan J. DeMent, Sang H. Dhong, Brian K. Flachs, Gilles Gervais, Iwao Takiguchi, Tetsuji Tamura
  • Publication number: 20090044030
    Abstract: Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamic clock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit.
    Type: Application
    Filed: October 6, 2008
    Publication date: February 12, 2009
    Inventors: Christopher Michael Abernathy, Gilles Gervais, Rolf Hilgendorf
  • Patent number: 7486096
    Abstract: In one embodiment, a test system tests a device under test (DUT). The DUT includes an internal test controller that executes built-in self-test (BIST programs. Built-in self-test programs include array-based automatic built-in self-test programs, discrete and combinational logic built-in self-test programs, and functional architecture verification programs (AVPs). An external manufacturing system test controller manages the internal test controller within the DUT and determines minimum operating voltage levels for a power supply input voltage that supplies the DUT. A logic simulator provides a modeling capability to further enhance the development of minimum voltage power supply input operational values for the DUT.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Sang H. Dhong, Brian Flachs, Gilles Gervais, Charles R. Johns, Brad W. Michael, Makoto Aikawa, Iwao Takiguchi, Tetsuji Tamura
  • Patent number: 7469357
    Abstract: Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamic clock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: December 23, 2008
    Assignee: International Business Machines Corporation
    Inventors: Christopher Michael Abernathy, Gilles Gervais, Rolf Hilgendork
  • Patent number: 7447602
    Abstract: A system and method for sorting processor chips based on a thermal design point are provided. With the system and method, for each processor chip, a high power workload is run on the processor chip to determine a voltage regulator module (VRM) load line. Thereafter, a thermal design point (TDP) workload is applied to the processor chip and the voltage is varied until a performance of the processor chip falls on the VRM load line. At this point, the power input to the processor chip is measured and used to sort, or bin, the processor chip. The various workloads applied have a constant frequency. From this sorting of processor chips, high speed processors that require less voltage to achieve a desired frequency and low current processors that drain less current while running at a desired frequency may be identified.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: November 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Douglas H. Bradley, Jonathan J. DeMent, Sang H. Dhong, Brian Flachs, Gilles Gervais, Yoichi Nishino
  • Publication number: 20080189090
    Abstract: A system and method for determining a guard band for an operating voltage of an integrated circuit device are provided. The system and method provide a mechanism for calculating the guard band based on a comparison of simulated noise obtained from a simulation of the integrated circuit device using a worst case waveform stimuli with simulated or measured power supply noise of a workload/test pattern that may be achieved using testing equipment. A scaling factor for the guard band is determined by comparing results of a simulation of a workload/test pattern with measured results of the workload/test pattern as applied to a hardware implementation of the integrated circuit device. This scaling factor is applied to a difference between the noise generated through simulation of the workload/test pattern and the noise generated through simulation of the worst case current waveform to generate a guard band value.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 7, 2008
    Inventors: Makoto Aikawa, Sang H. Dhong, Brian Flachs, Gilles Gervais, Yoichi Nishino, Iwao Takiguchi, Tetsuji Tamura, Yaping Zhou
  • Publication number: 20080168318
    Abstract: A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.
    Type: Application
    Filed: January 10, 2007
    Publication date: July 10, 2008
    Inventors: Jonathan J. DeMent, Sang H. Dhong, Gilles Gervais, Alain Loiseau, Kirk D. Peterson, John L. Sinchak
  • Publication number: 20080100328
    Abstract: In one embodiment, a test system tests a device under test (DUT). The DUT includes an internal test controller that executes built-in self-test (BIST programs. Built-in self-test programs include array-based automatic built-in self-test programs, discrete and combinational logic built-in self-test programs, and functional architecture verification programs (AVPs). An external manufacturing system test controller manages the internal test controller within the DUT and determines minimum operating voltage levels for a power supply input voltage that supplies the DUT. A logic simulator provides a modeling capability to further enhance the development of minimum voltage power supply input operational values for the DUT.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 1, 2008
    Applicant: IBM Corporation
    Inventors: Sang H. Dhong, Brian Flachs, Gilles Gervais, Charles R. Johns, Brad W. Michael, Makoto Aikawa, Iwao Takiguchi, Tetsuji Tamura
  • Publication number: 20080092006
    Abstract: A method and system for mitigating the impact of voltage supply variations on logic built-in self-test (LBIST) results. The method includes, but is not limited to: creating a set of customized LBIST activation patterns during IC design; propagating the activation patterns from the scan-able latches through the non-scan latches to the device under test; propagating the data from the device under test through the non-scan latches to the scan-able latches; capturing the data in a scan-able latch; and performing each test cycle independently such that the impact of voltage supply variations between test cycles is eliminated.
    Type: Application
    Filed: September 20, 2006
    Publication date: April 17, 2008
    Inventors: Nikhil Dakwala, Jonathan J. Dement, Sang H. Dhong, Brian Flachs, Gilles Gervais, Brad W. Michael