Abstract: The disclosure notably relates to a computer-implemented method of computing a visibility function of a 3D scene. The method includes obtaining a set of directions ({right arrow over (?)}) in the 3D scene, computing a set of lines that are parallel to the direction, for each computed set of lines, sampling the lines of the set into spatial segments, associating each line of a set with a bit field, each spatial segment of the line corresponding to a bit of the bit field, superimposing the set of lines and the 3D scene, when a spatial segment of a line intersects a geometry in the 3D scene, marking the bit, corresponding to the spatial segment of the bit field, associated with the line, obtaining two points in the 3D scene, identifying spatial segments having a closest alignment with the query segment, computing the visibility of the query segment by performing a logical bit operation.

Abstract: The disclosure notably relates to a computer-implemented method of computing a visibility function of a 3D scene. The method includes obtaining a set of directions ({right arrow over (?)}) in the 3D scene, computing a set of lines that are parallel to the direction, for each computed set of lines, sampling the lines of the set into spatial segments, associating each line of a set with a bit field, each spatial segment of the line corresponding to a bit of the bit field, superimposing the set of lines and the 3D scene, when a spatial segment of a line intersects a geometry in the 3D scene, marking the bit, corresponding to the spatial segment of the bit field, associated with the line, obtaining two points in the 3D scene, identifying spatial segments having a closest alignment with the query segment, computing the visibility of the query segment by performing a logical bit operation.

Abstract: The invention notably relates to a computer-implemented method for rendering the global illumination of a three-dimensional scene. The method comprises providing a 3D scene that comprises of a set of triangles and one or more direct light sources, determining that each triangle of the set has an area that is below a threshold, assigning to each triangle of the set a radius of influence using a probability law, obtaining a subset of triangles by filtering out the triangles according to their radius of influence, rendering the three-dimensional scene by lighting its set of triangles, the triangle of the subset of triangles being used as indirect light sources according to their radius of influence.

Abstract: The invention notably relates to a computer-implemented method for rendering the global illumination of a three-dimensional scene. The method comprises providing a 3D scene that comprises of a set of triangles and one or more direct light sources, determining that each triangle of the set has an area that is below a threshold, assigning to each triangle of the set a radius of influence using a probability law, obtaining a subset of triangles by filtering out the triangles according to their radius of influence, rendering the three-dimensional scene by lighting its set of triangles, the triangle of the subset of triangles being used as indirect light sources according to their radius of influence.

Abstract: Message send and receive blocks are provided to emulation ICs and reconfigurable interconnect ICs of an emulation system to reduce the multiplexed transfer latency of critical emulation signals. Each of a corresponding pair of a message send block and a message receive block is provided with a signal state value inclusion schedule to control operation of the message send and receive blocks. The signal state inclusion schedule calls for some signals within a message to be sent more often than other signals within the message. In some embodiments a parity value is implemented as part the message and included in the signal state inclusion schedule.

Abstract: Methods and apparatuses for emulating a circuit design that includes an in-circuit memory. Sets of reconfigurable logic resources are configured to emulate a logic element of a circuit, where the circuit may include a plurality of logic elements. A memory resource is configured to emulate a portion of the in-circuit memory. Reconfigurable interconnect resources are configured to interconnect the sets of configurable logic resources to the memory resource by way of a memory access arbiter. The memory access arbiter is configured to arbitrate and serialize accesses for the memory resource by the sets of reconfigurable logic resources in an emulation cycle, in accordance with associated priority levels. The priority level of the set of reconfigurable logic resources may be dependent on timing requirements of the set of reconfigurable logic resources and on timing characteristics of the associated logic element of the circuit.

Abstract: Message send and receive blocks are provided to emulation ICs and reconfigurable interconnect ICs of an emulation system to reduce the multiplexed transfer latency of critical emulation signals. Each of a corresponding pair of a message send block and a message receive block is provided with a signal state value inclusion schedule to control operation of the message send and receive blocks. The signal state inclusion schedule calls for some signals within a message to be sent more often than other signals within the message. In some embodiments a parity value is implemented as part the message and included in the signal state inclusion schedule.

Abstract: A method and system for compacting data and assignment to pins. A first sample of state data is received from a reconfigurable emulation resource. A set of the first sample of state data is stored into a first/current buffer. A second sample of state data is received. A determination is made as to whether the residual storage space of the first/current buffer is full and whether a set of the second sample needs to be portioned into two portions. The set of the second sample is stored in the first/current buffer to the extent it can be accommodated by the residual storage space of the first/current buffer. Any remaining portion of the set of the second sample is stored in a second/back-up buffer. Trace chains are assigned to trace pins based upon a schedule relating to the buffer fill rates.

Abstract: A novel reconfigurable logic element (RLE) architecture for use in an integrated circuit itself used in an emulation system is disclosed. The RLE has lookup table logic circuitry for implementing a function. In addition, the RLE contains multi-stage coupling logic circuitry correspondingly coupling RLE inputs to the inputs of the lookup table logic circuitry. This allows global routing of the emulation system by circuit design mapping software to be much more flexible, as the routing may be configured independently of those four input constraints due to the ability to reassign the inputs with the swapper.

Abstract: Methods and apparatuses for emulating a circuit design that includes an in-circuit memory. Sets of reconfigurable logic resources are configured to emulate a logic element of a circuit, where the circuit may include a plurality of logic elements. A memory resource is configured to emulate a portion of the in-circuit memory. Reconfigurable interconnect resources are configured to interconnect the sets of configurable logic resources to the memory resource by way of a memory access arbiter. The memory access arbiter is configured to arbitrate and serialize accesses for the memory resource by the sets of reconfigurable logic resources in an emulation cycle, in accordance with associated priority levels. The priority level of the set of reconfigurable logic resources may be dependent on timing requirements of the set of reconfigurable logic resources and on timing characteristics of the associated logic element of the circuit.

Abstract: Methods and systems for increasing the speed with which configuration data can be loaded and tested on a reconfigurable interconnect device are disclosed. A reconfigurable interconnect integrated circuit (IC), or a reconfigurable portion of an integrated circuit, is coupled to a digital storage circuit such as a shift register. A seed configuration pattern is loaded once into the digital storage circuit, which is loaded onto a first set of switches in the integrated circuit. The shift register shifts the configuration patterns by a predetermined amount, and then loads the shifted configuration pattern onto a second set of switches in the integrated circuit. Using the digital storage circuit coupled to the reconfigurable interconnect, each integrated circuit only needs to load a configuration pattern once, instead of reloading a new configuration pattern for each set of switches in the integrated circuit.