Patents by Inventor Gilles Pelissier
Gilles Pelissier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929748Abstract: A wobulated signal generator includes a chain of delay elements and control circuitry. The chain of delay elements includes first delay elements, second delay elements, and third delay elements. The control circuitry, in operation, enables a number of the first delay elements, disables a number of the third delay elements, and enables a selected number of the second delay elements, defining a period of time between two consecutive rising edges of a digital wobulated signal at an output of the wobulated signal generator. The control circuitry monitors an average frequency of the digitally wobulated signal, and selectively modifies the number of enabled first delay elements and the number of disabled third delay elements based on the monitored average frequency of the digitally wobulated signal.Type: GrantFiled: November 16, 2022Date of Patent: March 12, 2024Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Ugo Mureddu, Gilles Pelissier, Guillaume Reymond
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Patent number: 11698993Abstract: A unique hardware key is recorded a secure hardware environment. A first logic circuit of the secure hardware environment is configured to generate a unique derived key from said unique hardware key and at least one piece of information. The at least one piece of information relates to one or more of an execution context and a use of a secret key. The secure hardware environment further includes a first encryption device that performs a symmetric encryption of the secret key using the unique derived key. This symmetric encryption generates an encrypted secret key for use outside of the secure hardware environment.Type: GrantFiled: January 28, 2021Date of Patent: July 11, 2023Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: Gilles Pelissier, Nicolas Anquet, Delphine Le-Goascoz
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Patent number: 11610025Abstract: An integrated circuit includes a secure hardware environment having a first input that receives a key number. A key generation device generates a secret key from the key number and a unique key. A signature generation device generates a signature associated with the key number. A second input of the secure hardware environment receives encrypted binary data. A decryption device operates to decrypt the received encrypted binary data using the secret key. A third input the secure hardware environment receives an authentication signature. An authentication device authorizes use of the secret key to decrypt only if the signature generated by the signature generation device is identical to the authentication signature.Type: GrantFiled: January 28, 2021Date of Patent: March 21, 2023Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: Gilles Pelissier, Nicolas Anquet, Delphine Le-Goascoz
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Publication number: 20210240862Abstract: An integrated circuit includes a secure hardware environment having a first input that receives a key number. A key generation device generates a secret key from the key number and a unique key. A signature generation device generates a signature associated with the key number. A second input of the secure hardware environment receives encrypted binary data. A decryption device operates to decrypt the received encrypted binary data using the secret key. A third input the secure hardware environment receives an authentication signature. An authentication device authorizes use of the secret key to decrypt only if the signature generated by the signature generation device is identical to the authentication signature.Type: ApplicationFiled: January 28, 2021Publication date: August 5, 2021Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: Gilles PELISSIER, Nicolas ANQUET, Delphine LE-GOASCOZ
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Publication number: 20210240863Abstract: A unique hardware key is recorded a secure hardware environment. A first logic circuit of the secure hardware environment is configured to generate a unique derived key from said unique hardware key and at least one piece of information. The at least one piece of information relates to one or more of an execution context and a use of a secret key. The secure hardware environment further includes a first encryption device that performs a symmetric encryption of the secret key using the unique derived key. This symmetric encryption generates an encrypted secret key for use outside of the secure hardware environment.Type: ApplicationFiled: January 28, 2021Publication date: August 5, 2021Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: Gilles PELISSIER, Nicolas ANQUET, Delphine LE-GOASCOZ
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Patent number: 10140020Abstract: A method for transferring messages from a producer element to a consumer element uses a memory shared between the producer element and the consumer element, and a hardware queue including several registers designed to contain addresses of the shared memory. The method includes the steps of storing each message for the consumer element in the shared memory in the form of a node of a linked list, including a pointer to a next node in the list, the pointer being initially void, writing successively the address of each node in a free slot of the queue, whereby the node identified by each slot of the queue is the first node of a linked list assigned to the slot, and when the queue is full, writing the address of the current node in memory, in the pointer of the last node of the linked list assigned to the last slot of the queue, whereby the current node is placed at the end of the linked list assigned to the last slot of the queue.Type: GrantFiled: February 28, 2017Date of Patent: November 27, 2018Assignee: STMicroelectronics (Grenoble 2) SASInventors: Gilles Pelissier, Jean-Philippe Cousin, Badr Bentaybi
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Publication number: 20170168721Abstract: A method for transferring messages from a producer element to a consumer element uses a memory shared between the producer element and the consumer element, and a hardware queue including several registers designed to contain addresses of the shared memory. The method includes the steps of storing each message for the consumer element in the shared memory in the form of a node of a linked list, including a pointer to a next node in the list, the pointer being initially void, writing successively the address of each node in a free slot of the queue, whereby the node identified by each slot of the queue is the first node of a linked list assigned to the slot, and when the queue is full, writing the address of the current node in memory, in the pointer of the last node of the linked list assigned to the last slot of the queue, whereby the current node is placed at the end of the linked list assigned to the last slot of the queue.Type: ApplicationFiled: February 28, 2017Publication date: June 15, 2017Inventors: Gilles Pelissier, Jean-Philippe Cousin, Badr Bentaybi
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Patent number: 9594506Abstract: A method for transferring messages from a producer element to a consumer element uses a memory shared between the producer element and the consumer element, and a hardware queue including several registers designed to contain addresses of the shared memory. The method includes the steps of storing each message for the consumer element in the shared memory in the form of a node of a linked list, including a pointer to a next node in the list, the pointer being initially void, writing successively the address of each node in a free slot of the queue, whereby the node identified by each slot of the queue is the first node of a linked list assigned to the slot, and when the queue is full, writing the address of the current node in memory, in the pointer of the last node of the linked list assigned to the last slot of the queue, whereby the current node is placed at the end of the linked list assigned to the last slot of the queue.Type: GrantFiled: June 19, 2014Date of Patent: March 14, 2017Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Gilles Pelissier, Jean-Philippe Cousin, Badr Bentaybi
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Publication number: 20140379999Abstract: A method for transferring messages from a producer element to a consumer element uses a memory shared between the producer element and the consumer element, and a hardware queue including several registers designed to contain addresses of the shared memory. The method includes the steps of storing each message for the consumer element in the shared memory in the form of a node of a linked list, including a pointer to a next node in the list, the pointer being initially void, writing successively the address of each node in a free slot of the queue, whereby the node identified by each slot of the queue is the first node of a linked list assigned to the slot, and when the queue is full, writing the address of the current node in memory, in the pointer of the last node of the linked list assigned to the last slot of the queue, whereby the current node is placed at the end of the linked list assigned to the last slot of the queue.Type: ApplicationFiled: June 19, 2014Publication date: December 25, 2014Inventors: Gilles Pelissier, Jean-Philippe Cousin, Badr Bentaybi
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Patent number: 8606976Abstract: A data stream flow-controller controls a transfer of data between a data processing device and an interconnection network. The flow controller includes interfaces for interfacing the controller on the network side and on the processing device side, a configurable storage for buffering queues of data in the controller before transfer to destination, and a programmable controller to control the storage to define queue parameters.Type: GrantFiled: June 18, 2010Date of Patent: December 10, 2013Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics S.r.l.Inventors: Giuseppe Desoli, Jean-Philippe Cousin, Gilles Pelissier, Badr Bentaybi
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Patent number: 8015363Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.Type: GrantFiled: September 15, 2009Date of Patent: September 6, 2011Assignee: STMicroelectronics S.A.Inventors: Jean-Philippe Cousin, Jean-Jose Berenguer, Gilles Pelissier
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Patent number: 7971003Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.Type: GrantFiled: January 26, 2010Date of Patent: June 28, 2011Assignee: STMicroelectronics SAInventors: Jean-Philippe Cousin, Jean-Jose Berenguer, Gilles Pelissier
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Publication number: 20100325318Abstract: A data stream flow-controller controls a transfer of data between a data processing device and an interconnection network. The flow controller includes interfaces for interfacing the controller on the network side and on the processing device side, a configurable storage for buffering queues of data in the controller before transfer to destination, and a programmable controller to control the storage to define queue parameters.Type: ApplicationFiled: June 18, 2010Publication date: December 23, 2010Applicants: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.Inventors: Giuseppe Desoli, Jean-Philippe Cousin, Gilles Pelissier, Badr Bentaybi
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Publication number: 20100199051Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.Type: ApplicationFiled: January 26, 2010Publication date: August 5, 2010Applicant: STMICROELECTRONICS SAInventors: Jean-Philippe Cousin, Jean-Jose Berenguer, Gilles Pelissier
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Patent number: 7743217Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.Type: GrantFiled: June 27, 2006Date of Patent: June 22, 2010Assignee: STMicroelectronics S.A.Inventors: Jean-Philippe Cousin, Jean-José Berenguer, Gilles Pelissier
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Patent number: 7653788Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.Type: GrantFiled: April 4, 2006Date of Patent: January 26, 2010Assignee: STMicroelectronics SAInventors: Jean-Philippe Cousin, Jean-Jose Berenguer, Gilles Pelissier
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Publication number: 20100011171Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.Type: ApplicationFiled: September 15, 2009Publication date: January 14, 2010Applicant: STMicroelectronics S.A.Inventors: Jean-Philippe Cousin, Jean-Jose Berenguer, Gilles Pelissier
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Publication number: 20070016730Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.Type: ApplicationFiled: June 27, 2006Publication date: January 18, 2007Applicant: STMicroelectronics S.A.Inventors: Jean-Philippe Cousin, Jean-Jose Berenguer, Gilles Pelissier
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Publication number: 20060259705Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.Type: ApplicationFiled: April 4, 2006Publication date: November 16, 2006Applicant: STMICROELECTRONICS SAInventors: Jean-Philippe Cousin, Jean-Jose Berenguer, Gilles Pelissier