Abstract: A microelectronic circuit comprising: a stack of lower, intermediate and upper circuit tiers, a matrix of devices outputting and/or receiving analogue electrical signals, made in the upper circuit tier, an analogue amplification and/or processing circuit made in the lower circuit tier, a digital processing circuit made in the intermediate circuit tier, an analogue-to-digital and/or digital-to-analogue conversion circuit made in the lower and/or intermediate circuit tier, electrically coupled to the analogue circuit and the digital circuit, electrical interconnections passing through the intermediate circuit tier and coupling the analogue circuit to the devices.

Abstract: A method of processing an image including pixels distributed in cells and in blocks is disclosed, the method including the steps of: a) for each cell, generating n first intensity values of gradients having different orientations, each first value being a weighted sum of the values of the pixels of the cell; b) for each cell, determining a main gradient orientation of the cell and a second value representative of the intensity of the gradient in the main orientation; c) for each block, generating a descriptor of n values respectively corresponding, for each of the n gradient orientations, to the sum of the second values of the cells of the block having the gradient orientation considered as the main gradient orientation.

Abstract: A matrix-array sensor comprises a matrix of detection elements arranged in rows and columns and a readout circuit for each column, the elements of one and the same column linked to the corresponding readout circuit via a bus, each element comprising a sensor, a charge integrator configured to accumulate charge generated by the sensor, a comparator configured to generate a trigger signal when a voltage level across the terminals of this comparator reaches a threshold level, and a bus access logic circuit which is configured to receive, as input, the trigger signal and to attempt to transmit, over the bus, an address of the element in the column, wherein the elements of one and the same column have predetermined bus access priority levels, and wherein the bus access logic circuit of each element is configured: to abandon transmission of the address and reset the charge integrator of the detection element if the bus is pre-empted by an element having a higher priority level; to count the number of attempts made

Abstract: A method of processing an image including pixels distributed in cells and in blocks is disclosed, the method including the steps of: a) for each cell, generating n first intensity values of gradients having different orientations, each first value being a weighted sum of the values of the pixels of the cell; b) for each cell, determining a main gradient orientation of the cell and a second value representative of the intensity of the gradient in the main orientation; c) for each block, generating a descriptor of n values respectively corresponding, for each of the n gradient orientations, to the sum of the second values of the cells of the block having the gradient orientation considered as the main gradient orientation.

Abstract: A matrix-array sensor comprises a matrix of detection elements arranged in rows and columns and a readout circuit for each column, the elements of one and the same column linked to the corresponding readout circuit via a bus, each element comprising a sensor, a charge integrator configured to accumulate charge generated by the sensor, a comparator configured to generate a trigger signal when a voltage level across the terminals of this comparator reaches a threshold level, and a bus access logic circuit which is configured to receive, as input, the trigger signal and to attempt to transmit, over the bus, an address of the element in the column, wherein the elements of one and the same column have predetermined bus access priority levels, and wherein the bus access logic circuit of each element is configured: to abandon transmission of the address and reset the charge integrator of the detection element if the bus is pre-empted by an element having a higher priority level; to count the number of attempts made

Abstract: An image sensor having photosites forming an array (K×L) of K rows and L columns, including a first set of integrator circuits, with a first regulation by analog weighting in blocks of n×n? photosites, said photosites belonging to n adjacent columns and to n? adjacent rows, and a second set of integrator circuits, with a second regulation by analog weighting in blocks of m×m? photosites, said photosites belonging to m adjacent columns and to m? adjacent rows, n adjacent columns of a first set of columns of the array being connected to n×n? integrator circuits of the first set, m adjacent columns of a second set of columns of the array being connected to m×m? integrator circuits of the second set, n columns of the first set alternating with m columns of the second set to form the array of photosites.

Abstract: An image sensor having photosites forming an array (K×L) of K rows and L columns, including a first set of integrator circuits, with a first regulation by analog weighting in blocks of n×n? photosites, said photosites belonging to n adjacent columns and to n? adjacent rows, and a second set of integrator circuits, with a second regulation by analog weighting in blocks of m×m? photosites, said photosites belonging to m adjacent columns and to a adjacent rows, n adjacent columns of a first set of columns of the array being connected to n×n? integrator circuits of the first set, on adjacent columns of a second set of columns of the array being connected to m×m? integrator circuits of the second set, n columns of the first set alternating with on columns of the second set to form the array of photosites.