Patents by Inventor Gilman D. Chesley

Gilman D. Chesley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4354207
    Abstract: System for identifying and locating analog information recorded on a serial access read/write medium. In some embodiments, the analog signal is sampled by scanning the medium, and a memory is employed to normalize the rate at which the sampled signals are output. In one embodiment, the memory is also utilized to compress the sampled signals, and in another, externally generated identifying information is recorded with the analog information.
    Type: Grant
    Filed: March 12, 1979
    Date of Patent: October 12, 1982
    Inventor: Gilman D. Chesley
  • Patent number: 4333142
    Abstract: Computer and memory system on a wafer which contains redundant elements and which is capable of self-testing and self-configuration to form a complete system consisting of a central processing unit (CPU), a read only memory unit (ROM), and a plurality of read/write random access memory units (RAM). These units are interconnected by a common bus, which is also available for external connections to the wafer. The first CPU tests each ROM to find a good one and then uses the program contained in that ROM to test itself. If the first CPU does not test satisfactorily, the remaining CPU's are tested until a good one is found. The RAM's are then tested with the good ROM and CPU, and the results are tabulated to form a page oriented computer system.
    Type: Grant
    Filed: July 12, 1979
    Date of Patent: June 1, 1982
    Inventor: Gilman D. Chesley
  • Patent number: 4191996
    Abstract: Computer and memory system on a wafer which contains redundant elements and which is capable of self-testing and self-configuration to form a complete system consisting of a central processing unit (CPU), a read only memory unit (ROM), and a plurality of read/write random access memory units (RAM). These units are interconnected by a common bus, which is also available for external connections to the wafer. The first CPU tests each ROM to find a good one and then uses the program contained in that ROM to test itself. If the first CPU does not test satisfactorily, the remaining CPU's are tested until a good one is found. The RAM's are then tested with the good ROM and CPU, and the results are tabulated to form a page oriented computer system.
    Type: Grant
    Filed: July 22, 1977
    Date of Patent: March 4, 1980
    Inventor: Gilman D. Chesley
  • Patent number: 4134357
    Abstract: Pneumatic tire having an integral inflation indicator in the form of interdigitized groups of raised mesas affixed to the sidewall of the casing on opposite sides of the centerline of the sidewall. The two groups pivot apart by flexing of the sidewall under load when the tire is under-inflated, and they tend to overlap at the centerline when the tire is over-inflated. Indicators carried by the mesas indicate by position the extent of under-inflation or over-inflation.
    Type: Grant
    Filed: October 28, 1977
    Date of Patent: January 16, 1979
    Inventor: Gilman D. Chesley
  • Patent number: 4055754
    Abstract: Integrated circuit memory device and method of testing the same wherein test logic is included in the device for detecting the presence of predetermined patterns applied to the memory cells. The cells are tested in groups to reduce the amount of time required for the test.
    Type: Grant
    Filed: December 22, 1975
    Date of Patent: October 25, 1977
    Inventor: Gilman D. Chesley
  • Patent number: 4038648
    Abstract: A self-configurable circuit structure and method for forming the same, for achieving wafer scale integration including the combination of an integrated circuit wafer having an input and an output, wafer control means to provide test and operational modes, at least one unit circuit on the wafer connected to the wafer control means, coupled between the wafer input and output. The unit circuit includes a semi-conductor chip, test means for functional testing of the chip and circuit control means responsive to the output of the test means to intercouple the unit circuit if it is properly functioning between the wafer input and output to form a functional circuit.
    Type: Grant
    Filed: June 3, 1974
    Date of Patent: July 26, 1977
    Inventor: Gilman D. Chesley