Abstract: A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency prediction unit, and a variable-latency datapath. The adaptive voltage scaling unit generates a plurality of operation voltages and transmits the operation voltages to the variable-latency datapath. The variable-latency datapath operates with different latencies according to the operation voltages and generates an operation latency. The latency prediction unit receives the operation latency and a system latency tolerance and generates a voltage scaling signal for the adaptive voltage scaling unit according to the operation latency and the system latency tolerance. The adaptive voltage scaling unit outputs and scales the operation voltages thereof according to the voltage scaling signal.

Abstract: A transmission method executed in a multiple input multiple output wireless communication system may include the following steps: receiving a transmitting bit sequence; providing an X level pulse amplitude modulation (X-PAM) signal set, wherein distances between any two adjacent signal points in the X-PAM are the same; generating M signal sets according to the X-PAM signal set, wherein the ith signal set is formed by multiplying the X-PAM signal set with a parameter (1/X)(i?1), wherein i is an integer from 1 to M, and generating a X-PAM signal set joint coding/decoding table according a superposition result of the M signal sets; generating M transmitting bit sub-sequences according to the transmitting bit sequence; generating M transmitting signals according to the M transmitting bit sub-sequences and the X-PAM signal set joint coding/decoding table; transmitting the M transmitting signals to a wireless transmission channel via M transmitting antennae.

Abstract: A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency prediction unit, and a variable-latency datapath. The adaptive voltage scaling unit generates a plurality of operation voltages and transmits the operation voltages to the variable-latency datapath. The variable-latency datapath operates with different latencies according to the operation voltages and generates an operation latency. The latency prediction unit receives the operation latency and a system latency tolerance and generates a voltage scaling signal for the adaptive voltage scaling unit according to the operation latency and the system latency tolerance. The adaptive voltage scaling unit outputs and scales the operation voltages thereof according to the voltage scaling signal.

Abstract: A frequency synthesizer for generating a plurality of frequencies of a MB-OFDM UWB system is disclosed, wherein the frequencies include first to fourteenth frequencies from low to high and any of the adjacent two frequencies differs by a basic intervallic frequency. The frequency synthesizer includes a phase locked loop generating an initial signal with a frequency equal to the second frequency, an intervallic frequency generator generating first to third intervallic frequencies from low to high and all being integers times the basic intervallic frequency and generating a forth intervallic frequency equal to the basic intervallic frequency, and first to third mixers connected in series, respectively receiving the fourth intervallic frequency, one of the first to third intervallic, and the first intervallic frequency, to respectively generate the first to third frequencies, the fourth to ninth and the thirteenth to fourteenth frequencies, and the tenth to twelfth frequencies.

Abstract: A two-piece wireless hearing improvement system having a pocket piece and an earpiece, wherein the pocket piece includes a microphone adapted to receive analog signals, a first processor coupled to the microphone to convert the analog signals to digital signals, and a first transceiver coupled to the processor to transmit the digital signals. The earpiece includes a second transceiver for receiving the digital signals, a second processor coupled to the second transceiver for converting the digital signals to analog signals, a speaker coupled to the second processor for transmitting the analog signals, and a movement detector for detecting relative movements between the earpiece and the pocket piece and generating a first signal according to the relative movements. The first processor provides signal compensation based on the first signal.

Abstract: A transmission method executed in a multiple input multiple output wireless communication system may include the following steps: receiving a transmitting bit sequence; providing an X level pulse amplitude modulation (X-PAM) signal set, wherein distances between any two adjacent signal points in the X-PAM are the same; generating M signal sets according to the X-PAM signal set, wherein the ith signal set is formed by multiplying the X-PAM signal set with a parameter (1/X)(i-1), wherein i is an integer from 1 to M, and generating a X-PAM signal set joint coding/decoding table according a superposition result of the M signal sets; generating M transmitting bit sub-sequences according to the transmitting bit sequence; generating M transmitting signals according to the M transmitting bit sub-sequences and the X-PAM signal set joint coding/decoding table; transmitting the M transmitting signals to a wireless transmission channel via M transmitting antennae.

Abstract: An ultra-wideband (UWB) transceiver for use in UWB communication includes a voltage-controlled oscillator (VCO) configured to periodically and sequentially generate a series of base frequencies based on a predetermined sequence and a waveform generator to generate carrier waves based on the generated base frequencies.

Abstract: A digital signal processor structure by performing length-scalable Fast Fourier Transformation (FFT) discloses a single processor element (single PE), and a simple and effective address generator are used to achieve length-scalable, high performance, and low power consumption in split-radix-2/4 FFT or IFFT module. In order to meet different communication standards, the digital signal processor structure has run-time configuration to perform for different length requirements. Moreover, its execution time can fit the standards of Fast Fourier Transformation (FFT) or Inverse Fast Fourier Transformation (IFFT).

Abstract: A communication system comprising a channel encoder to generate a binary bit stream, a mapping unit coupled to the channel encoder, the mapping unit configured to receive the binary bit stream from the channel encoder and to map every “n” consecutive bits of the binary bit stream into a symbol in accordance with a mapping table, wherein the symbol has a symbol value related to a modulation mode, “n” being a positive integer, and a number of “m” modulation units coupled to the mapping unit, “m” being a positive integer, the modulation units configured to receive a set of “m” symbols from the mapping unit and modulate the set of “m” symbols based on the modulation mode, wherein a combined value of the symbol values of the set of “m” symbols from the mapping unit is distinguishable from another combined value of the symbol values of another set of “m” symbols from the mapping unit, and wherein a combined value of the symbol values of a set of “m” symbols from the mapping unit corresponds to a distinguishable bit

Abstract: A method for power management in a communication system is disclosed. The communication system is capable of operating in a first mode, and comprises at least one device having first module corresponding to the first mode. The device can be configured to a normal mode or a power saving mode. First, map data is retrieved from frame data, in which the map data indicates a first time point corresponding to the first mode. Then, when the communication system operates in the first mode, the first module of the device is determined to be configured to the normal mode or the power saving mode according to the first time point.

Abstract: A communications system that comprises a channel encoder for encoding a plurality of information bits, a mapping unit coupled to the channel encoder for mapping the plurality of information bits into a first set of quadrature phase shift keying (QPSK) symbols and a second set of QPSK symbols, wherein every successive predetermined number of information bits are mapped to a first QPSK symbol and a second QPSK symbol in one symbol period in accordance with a mapping table, a first modulation unit coupled to the mapping unit for converting the first QPSK symbol into a first QPSK constellation symbol, and a second modulation coupled to the mapping unit for converting the second QPSK symbol into a second QPSK constellation symbol.

Abstract: A frequency synthesizer for generating a plurality of frequencies of a MB-OFDM UWB system is disclosed, wherein the frequencies include first to fourteenth frequencies from low to high and any of the adjacent two frequencies differs by a basic intervallic frequency. The frequency synthesizer includes a phase locked loop generating an initial signal with a frequency equal to the second frequency, an intervallic frequency generator generating first to third intervallic frequencies from low to high and all being integers times the basic intervallic frequency and generating a forth intervallic frequency equal to the basic intervallic frequency, and first to third mixers connected in series, respectively receiving the fourth intervallic frequency, one of the first to third intervallic, and the first intervallic frequency, to respectively generate the first to third frequencies, the fourth to ninth and the thirteenth to fourteenth frequencies, and the tenth to twelfth frequencies.

Abstract: A two-piece wireless hearing improvement system having a pocket piece and an earpiece, wherein the pocket piece includes a microphone adapted to receive analog signals, a first processor coupled to the microphone to convert the analog signals to digital signals, and a first transceiver coupled to the processor to transmit the digital signals. The earpiece includes a second transceiver for receiving the digital signals, a second processor coupled to the second transceiver for converting the digital signals to analog signals, a speaker coupled to the second processor for transmitting the analog signals, and a movement detector for detecting relative movements between the earpiece and the pocket piece and generating a first signal according to the relative movements. The first processor provides signal compensation based on the first signal.

Abstract: An ultra-wideband (UWB) transceiver for use in UWB communication includes a voltage-controlled oscillator (VCO) configured to periodically and sequentially generate a series of base frequencies based on a predetermined sequence and a waveform generator to generate carrier waves based on the generated base frequencies.

Abstract: A digital signal processor structure by performing length-scalable Fast Fourier Transformation (FFT) discloses a single processor element (single PE), and a simple and effective address generator are used to achieve length-scalable, high performance, and low power consumption in split-radix-2/4 FFT or IFFT module. In order to meet different communication standards, the digital signal processor structure has run-time configuration to perform for different length requirements. Moreover, its execution time can fit the standards of Fast Fourier Transformation (FFT) or Inverse Fast Fourier Transformation (IFFT).

Abstract: A communications system that comprises a channel encoder for encoding a plurality of information bits, a mapping unit coupled to the channel encoder for mapping the plurality of information bits into a first set of quadrature phase shift keying (QPSK) symbols and a second set of QPSK symbols, wherein every successive predetermined number of information bits are mapped to a first QPSK symbol and a second QPSK symbol in one symbol period in accordance with a mapping table, a first modulation unit coupled to the mapping unit for converting the first QPSK symbol into a first QPSK constellation symbol, and a second modulation coupled to the mapping unit for converting the second QPSK symbol into a second QPSK constellation symbol.

Abstract: A transport protocol that meets the requirements and performance for multimedia data transfer in a wireless link includes a transmitting/sending station and a receiving station. The inventive protocol is referred to as the Burst-oriented Transport with Time-bounded Retransmission (BTTR). This scheme uses a large transmission window for sending/receiving a burst of time-sensitive data and, within this window, several smaller observation windows are used for dynamic error retransmission. There is a time limitation on each retransmission such that the burst of data can be received in a timely manner, and thus trading some packet losses (still in an acceptable range) for delay and throughput performance. Specifically, the wireless network includes a wireless station for transmitting data over a wireless link. The sending station transmits a plurality of sequential data packets to the receiving station, wherein each plurality of sequential data packets form a respective Group-of-Packet (GOP).

Abstract: A scalable server architecture for use in implementing scaled media servers capable of simultaneous real-time data stream retrieval for large numbers of subscribers. A scalable server includes a plurality of stream pumping engines each accessing a particular storage device of a storage subsystem, and a server processor which receives retrieval requests from subscribers and directs the stream pumping engines to retrieve the requested data streams. Each of the stream pumping engines may include a storage controller coupled to its corresponding storage device for directing retrieval of the requested stream therefrom, a network controller for supplying the retrieved stream to a client network, and a processor for directing the operation of the storage and network controllers. Each of the stream pumping engines may also include a shared memory accessible by the corresponding stream pumping engine processor and the server processor.

Abstract: A cable network is provided with at least one bridge that is connected to a first cable segment of the cable network. The bridge receives from a shared communication medium a first carrier signal, having a first carrier frequency that is allocated for intra cable segment packet communication, containing packets modulated thereon. The bridge demodulates selected packets originating in the first cable segment from the first carrier signal. The bridge modulates each of the demodulated packets, that are destined outside of the first cable segment, onto a second carrier signal having a second carrier frequency. The bridge then transmits the second carrier signal on an upstream link of the common shared medium.

Abstract: A system and method are provided for routing received cells through a switch fabric. A plurality of output channels are organized into a plurality of channel groups, wherein each of the channels groups is associated with one or more unique output ports of a Benes network. A plurality of cells destined to one or more of the plurality of channel groups is received at plural input queues. A different output port of the Benes network is selected for one or more of the input queues that contains a cell. Then, one cell is switched from each of one or more input queues through the Benes network to the respective selected output port.