Abstract: An apparatus includes an integrated circuit that includes an in-circuit power switch coupled to a power supply node, a functional circuit coupled between the in-circuit power switch and a ground node, a test circuit, and a test power switch coupled to the test circuit, wherein the test power switch is a replica of the in-circuit power switch. The test circuit is configured to determine characteristics of the test power switch, and to measure a voltage difference across the in-circuit power switch. The test circuit is also configured to use the characteristics of the test power switch and the voltage difference to determine a power consumption of the functional circuit.

Abstract: An apparatus includes an integrated circuit that includes an in-circuit power switch coupled to a power supply node, a functional circuit coupled between the in-circuit power switch and a ground node, a test circuit, and a test power switch coupled to the test circuit, wherein the test power switch is a replica of the in-circuit power switch. The test circuit is configured to determine characteristics of the test power switch, and to measure a voltage difference across the in-circuit power switch. The test circuit is also configured to use the characteristics of the test power switch and the voltage difference to determine a power consumption of the functional circuit.

Abstract: A circuit including control logic; and configurable impedance logic, operatively coupled to the control logic, comprising a configurable transistor structure operative to selectively change from a high impedance mode where the configurable transistor structure is configurable as a plurality of series connected diodes having their cathodes coupled together, and a low impedance mode where the configurable transistor structure is configurable to include a plurality of cascoded transistors. The circuit may further include at least one control signal line from the control logic to the configurable impedance logic, where the control signal line is operative to provide a control signal for configuring the configurable impedance logic.

Abstract: An analog debugging block of an integrated circuit includes a multiplexor, a buffer, and a voltage-controlled oscillator. An analog voltage signal-of-interest is selectively passed through the multiplexor to the buffer. The buffer outputs an analog control voltage dependent on the selected analog voltage signal-of-interest. The analog control voltage serves as an input to the voltage-controlled oscillator and is used to control a frequency of a digital output signal generated from the voltage-controlled oscillator. The digital output signal from the voltage-controlled oscillator is driven off-chip, whereupon a frequency of the digital output signal is determined and compared against a collection of known frequencies that correspond to particular known voltages of the analog voltage signal-of-interest, thereby resulting in a determination of the value of the selected analog voltage signal-of-interest.

Abstract: A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the effects of aging. In an alternate embodiment, the power supply voltage control codes can be increased or decreased to compensate for aging effects. In another embodiment, a ring oscillator is used to approximate the effects of NBTI. In this embodiment, the frequency domain is converted to time domain using digital counters and programmable power supply control words are used to change the operating parameters of the power supply to compensate for aging effects.

Abstract: A method and apparatus for sensing an aging effect on an integrated circuit using a sensor disposed on the integrated circuit and arranged to generate an output dependent on a condition of an element within the sensor. A processor operatively connected to the sensor is arranged to indicate a code dependent the output.

Abstract: A method for synchronizing a data signal and a clock signal has been developed. The method first generates two separate intermediate data signals. The intermediate data signals lag the input data signal. The separate durations of the two lagging signals are combined to form an output data signal that is synchronized with the system clock signal.

Abstract: A temperature monitoring technique that eliminates the need for bipolar devices. In one embodiment of the present invention, a long-channel MOS transistor is configured in a diode connection to sense change in temperature. The diode drives a linear regulator and an oscillator. The oscillator in turn drives a counter, which counts pulses for a fixed period of time. The system clock on the chip is used as a temperature-independent frequency to generate a count. The temperature-dependent frequency is counted for a fixed number of system clock cycles. The present invention eliminates band gap circuitry currently used in most thermal sensing devices to provide a temperature-independent reference.

Abstract: A clock frequency multiplier design is provided. The clock frequency multiplier includes an input stage arranged to receive an input clock signal, a first clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a first signal dependent on a low phase of the input clock signal, a second clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a second signal dependent on a high phase of the input clock signal, and an output stage operatively connected to the first clock cycle generator stage and the second clock cycle generator stage and arranged to output a high pulse on an output clock signal for every low pulse on the first signal and the second signal.

Abstract: A method and apparatus for monitoring a temperature on an integrated circuit that includes a thin gate oxide transistor. A temperature monitoring system that includes a thick gate oxide transistor is provided. The temperature monitoring system includes a temperature independent voltage generator, a temperature dependent voltage generator that includes a thick gate oxide transistor, and a quantifier operatively connected to the temperature independent voltage generator and temperature dependent voltage generator.

Abstract: A charge pump is arranged to generate a current dependent on a phase difference between a first signal and a second signal. A reference circuit is operatively connected to the charge pump and arranged to adjust the charge pump so that the charge pump is independent of an aging effect.

Abstract: A bias generator adjustment system adjusts a PLL or DLL bias generator dependent on negative bias temperature instability effects in an integrated circuit. The bias generator adjustment system uses an aging independent reference circuit and a bias circuit to operatively adjust a bias generator such that transistor ‘aging’ effects that occur over the lifetime of an integrated circuit are compensated for or corrected.

Abstract: A single edge-triggered flip-flop having an asynchronous programmable reset function is provided. Using an externally generated reset value, the single edge-triggered flip-flop may be asynchronously programmed to dynamically reset to either a logical high or a logical low. Further, a single edge-triggered flip-flop having a reduced hold time is provided. In particular, by inputting a clock signal into a slave stage of the single edge-triggered flip-flop before inputting the clock signal into a master stage of the single edge-triggered flip-flop, the single edge-triggered flip-flop's hold time may be reduced without negatively increasing a setup time of the single edge-triggered flip-flop.

Abstract: A bias generator adjustment system adjusts a PLL or DLL bias generator dependent on negative bias temperature instability effects in an integrated circuit. The bias generator adjustment system uses an aging independent reference circuit and a bias circuit to operatively adjust a bias generator such that transistor ‘aging’ effects that occur over the lifetime of an integrated circuit are compensated for or corrected.

Abstract: A method and apparatus for monitoring a temperature on an integrated circuit that includes a thin gate oxide transistor. A temperature monitoring system that includes a thick gate oxide transistor is provided. The temperature monitoring system includes a temperature independent voltage generator, a temperature dependent voltage generator that includes a thick gate oxide transistor, and a quantifier operatively connected to the temperature independent voltage generator and temperature dependent voltage generator.

Abstract: A method and apparatus for sensing an aging effect on an integrated circuit using a sensor disposed on the integrated circuit and arranged to generate an output dependent on a condition of an element within the sensor. A processor operatively connected to the sensor is arranged to indicate a code dependent the output.

Abstract: A charge pump is arranged to generate a current dependent on a phase difference between a first signal and a second signal. A reference circuit is operatively connected to the charge pump and arranged to adjust the charge pump so that the charge pump is independent of an aging effect.

Abstract: A clock frequency multiplier design is provided. The clock frequency multiplier includes an input stage arranged to receive an input clock signal, a first clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a first signal dependent on a low phase of the input clock signal, a second clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a second signal dependent on a high phase of the input clock signal, and an output stage operatively connected to the first clock cycle generator stage and the second clock cycle generator stage and arranged to output a high pulse on an output clock signal for every low pulse on the first signal and the second signal.

Abstract: A dual edge-triggered flip-flop that may be programmably reset independent of a clock signal is provided. Using an externally generated reset value, the dual edge-triggered flip-flop may be asynchronously programmed to reset to either a logical high or a logical low. Further, a dual edge-triggered flip-flop that may be set to multiple triggering modes is provided. Using an externally generated enable signal, the dual edge-triggered flip-flop may be set to function as a single edge-triggered or a dual edge-triggered device. Thus, the dual edge-triggered flip-flop may be used multiple types of computing environments.

Abstract: An integrated circuit has a plurality of sections, each having a phase detector and a control delay circuit. The phase detector, in response to a phase difference between a reference clock signal and a feedback signal from a portion of a clock grid, controls the delay of its associated clock delay circuit, which, in turn, outputs to the portion of the clock grid. The feedback signal to the phase detector may be connected to an output of a DLL or another portion of the clock grid controlled by a clock delay circuit not associated with the phase detector. Such an arrangement on the integrated circuit leads to clock grid skew reduction.