Patents by Inventor Gina M. Sparacino

Gina M. Sparacino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit input/output ESD protection circuit with gate voltage regulation and parasitic zener and junction diode
    Patent number: 5815360
    Abstract: An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: September 29, 1998
    Assignee: LSI Logic Corporation
    Inventors: Rosario Consiglio, Gina M. Sparacino
  • Process for providing electrostatic discharge protection to an integrated circuit output pad
    Patent number: 5707886
    Abstract: An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: January 13, 1998
    Assignee: LSI Logic Corporation
    Inventors: Rosario Consiglio, Gina M. Sparacino
  • Integrated circuit input/output ESD protection circuit with gate voltage regulation and parasitic zener and junction diode
    Patent number: 5594611
    Abstract: An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.
    Type: Grant
    Filed: January 12, 1994
    Date of Patent: January 14, 1997
    Assignee: LSI Logic Corporation
    Inventors: Rosario Consiglio, Gina M. Sparacino