Abstract: An apparatus and a method for synchronizing output clock signals across a plurality of phase-locked loops (PLLs). The apparatus coupled within each PLL comprises: a local counter configured to provide a count when receiving a reference clock signal; a comparator configured to compare the count from the local counter with a predetermined or preconfigured value; wherein a multiplexor connected to the local counter and counters of adjacent PLLs, configured to select the count from the local counter or a count from the counters of the adjacent PLLs; wherein the selected count from the multiplexor is incremented and directed to the local counter; wherein an output clock divider enable is asserted to the PLL to start an output clock divider to generate the output clock signal when the count from the local counter reaches the predetermined or preconfigured value.