Patents by Inventor Giorgia Longobardi
Giorgia Longobardi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10964806Abstract: A heterojunction power device includes a substrate; a III-nitride semiconductor region over the substrate; a source operatively connected to the semiconductor region; a drain operatively connected to the semiconductor region; a gate between the source and drain and over the semiconductor region. The source is in contact with a first portion located between the source and gate and having a two dimensional carrier gas. The drain is in contact with a second portion located between the drain and gate and having a two dimensional carrier gas. At least one of the first and second portions has a trench having vertical sidewalls and formed within the semiconductor region; mesa regions extend away from each sidewall of the trench. The two dimensional carrier gas is located alongside the mesa regions and the trench. At least one of the source and drain is in contact with the respective two dimensional carrier gas.Type: GrantFiled: May 24, 2019Date of Patent: March 30, 2021Assignee: CAMBRIDGE ENTERPRISE LIMITEDInventors: Giorgia Longobardi, Florin Udrea
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Publication number: 20200357907Abstract: We disclose a III-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first gate terminal formed over the first III-nitride semiconductor region between the first terminal and the second terminal.Type: ApplicationFiled: May 7, 2019Publication date: November 12, 2020Inventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
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Publication number: 20200357909Abstract: We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on thType: ApplicationFiled: May 7, 2019Publication date: November 12, 2020Inventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
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Publication number: 20200357906Abstract: We disclose herein a depletion mode III-nitride semiconductor based heterojunction device, comprising: a substrate; a III-nitride semiconductor region formed over the substrate, wherein the III-nitride semiconductor region comprises a heterojunction comprising at least one two-dimensional carrier gas of second conductivity type; a first terminal operatively connected to the III-nitride semiconductor region; a second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the III-nitride semiconductor region; at least two highly doped semiconductor regions of a first conductivity type formed over the III-nitride semiconductor region, the at least two highly doped semiconductor regions being formed between the first terminal and the second terminal; and a gate terminal formed over the at least two highly doped semiconductor regions; wherein the at least two highly doped semiconductor regions are spaced from each other in a second dimension.Type: ApplicationFiled: May 7, 2019Publication date: November 12, 2020Inventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
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Patent number: 10818786Abstract: We disclose a III-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first gate terminal formed over the first III-nitride semiconductor region between the first terminal and the second terminal.Type: GrantFiled: May 7, 2019Date of Patent: October 27, 2020Assignee: CAMBRIDGE GAN DEVICES LIMITEDInventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
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Publication number: 20200335493Abstract: The disclosure relates to a III-nitride power semiconductor based heterojunction device including a low voltage terminal, a high voltage terminal, a control terminal and an active heterojunction transistor formed on a substrate, and further including the following monolithically integrated components: voltage clamp circuit configured to limit a maximum potential that can be applied to the internal gate terminal, an on-state circuit configured to control the internal gate terminal of the active heterojunction transistor during an on-state operation, a turn-off circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-off operation and during an off-state.Type: ApplicationFiled: July 2, 2020Publication date: October 22, 2020Inventors: Martin ARNOLD, Loizos EFTHYMIOU, David Bruce VAIL, John William FINDLAY, Giorgia LONGOBARDI, Florin UDREA
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Publication number: 20200287536Abstract: A device includes a heterojunction device, a unipolar power transistor operatively connected in series with said hetero junction device; an external control terminal for driving said unipolar power transistor and said heterojunction device; and an interface unit having a plurality of interface terminals. A first interface terminal is operatively connected to an active gate region of the heterojunction device and a second interface terminal is operatively connected to said external control terminal. The heterojunction device includes a threshold voltage less than a threshold voltage of the unipolar power transistor, wherein the threshold voltage of the heterojunction device is less than a blocking voltage of the unipolar power transistor.Type: ApplicationFiled: May 20, 2020Publication date: September 10, 2020Inventors: Florin UDREA, Loizos EFTHYMIOU, Giorgia LONGOBARDI, Martin ARNOLD
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Publication number: 20200168599Abstract: The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary gate terminal (15) and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device (205) and a low-voltage auxiliary GaN device (210) wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.Type: ApplicationFiled: July 13, 2018Publication date: May 28, 2020Inventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi
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Patent number: 10593826Abstract: We disclose herewith a heterostructure-based infra-red (IR) device comprising a substrate comprising an etched portion and a substrate portion; a device region on the etched portion and the substrate portion, the device region comprising a membrane region which is an area over the etched portion of the substrate. At least one heterostructure-based element is formed at least partially within or on the membrane region and the heterostructure-based element comprises at least one two dimensional carrier gas.Type: GrantFiled: March 28, 2018Date of Patent: March 17, 2020Assignee: CAMBRIDGE GAN DEVICES LIMITEDInventors: Florin Udrea, Andrea De Luca, Giorgia Longobardi
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Patent number: 10483356Abstract: A power semiconductor device and method for making same are disclosed. The device includes a source bonding pad and a drain bonding pad, a drain metallization structure including a drain field plate connected to the drain bonding pad, and a source metallization structure comprising a source field plate connected to the source bonding pad. At least a portion of at least one of the bonding pads is situated directly over an active area. A dimension of at least one of the field plates varies depending upon the structure adjacent to the field plate.Type: GrantFiled: February 27, 2018Date of Patent: November 19, 2019Assignee: SILICONIX INCORPORATEDInventors: Max Shih-kuan Chen, Hao-Che Chien, Loizos Efthymiou, Florin Udrea, Giorgia Longobardi, Gianluca Camuso
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Publication number: 20190301906Abstract: We disclose herewith a heterostructure-based sensor comprising a substrate comprising an etched portion and a substrate portion; a device region located on the etched portion and the substrate portion; the device region comprising at least one membrane region which is an area over the etched portion of the substrate. At least one heterostructure-based element is located at least partially within or on the at least one membrane region, the heterostructure-based element comprising at least one two dimensional (2D) carrier gas.Type: ApplicationFiled: March 28, 2019Publication date: October 3, 2019Inventors: Florin Udrea, Andrea De Luca, Giorgia Longobardi
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Publication number: 20190305175Abstract: We disclose herewith a heterostructure-based infra-red (IR) device comprising a substrate comprising an etched portion and a substrate portion; a device region on the etched portion and the substrate portion, the device region comprising a membrane region which is an area over the etched portion of the substrate. At least one heterostructure-based element is formed at least partially within or on the membrane region and the heterostructure-based element comprises at least one two dimensional carrier gas.Type: ApplicationFiled: March 28, 2018Publication date: October 3, 2019Inventors: Florin Udrea, Andrea De Luca, Giorgia Longobardi
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Publication number: 20190288101Abstract: A heterojunction power device includes a substrate; a III-nitride semiconductor region over the substrate; a source operatively connected to the semiconductor region; a drain operatively connected to the semiconductor region; a gate between the source and drain and over the semiconductor region. The source is in contact with a first portion located between the source and gate and having a two dimensional carrier gas. The drain is in contact with a second portion located between the drain and gate and having a two dimensional carrier gas. At least one of the first and second portions has a trench having vertical sidewalls and formed within the semiconductor region; mesa regions extend away from each sidewall of the trench. The two dimensional carrier gas is located alongside the mesa regions and the trench. At least one of the source and drain is in contact with the respective two dimensional carrier gas.Type: ApplicationFiled: May 24, 2019Publication date: September 19, 2019Inventors: Giorgia LONGOBARDI, Florin UDREA
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Publication number: 20190267482Abstract: The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.Type: ApplicationFiled: May 7, 2019Publication date: August 29, 2019Inventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
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Publication number: 20190267456Abstract: A power semiconductor device and method for making same are disclosed. The device includes a source bonding pad and a drain bonding pad, a drain metallization structure including a drain field plate connected to the drain bonding pad, and a source metallization structure comprising a source field plate connected to the source bonding pad. At least a portion of at least one of the bonding pads is situated directly over an active area. A dimension of at least one of the field plates varies depending upon the structure adjacent to the field plate.Type: ApplicationFiled: February 27, 2018Publication date: August 29, 2019Applicant: SILICONIX INCORPORATEDInventors: Max Shih-kuan Chen, Hao-Che Chien, Loizos Efthymiou, Florin Udrea, Giorgia Longobardi, Gianluca Camuso
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Publication number: 20180269282Abstract: A semiconductor device includes a type IV semiconductor base substrate, a first type III-V semiconductor layer formed on a first surface of the base substrate, and a second type III-V semiconductor layer with a different bandgap as the first type III-V being formed on the first type III-V semiconductor layer. The semiconductor device further includes first and second electrically conductive device terminals each being formed on the second type III-V semiconductor layer and each being in ohmic contact with the two-dimensional charge carrier gas. The base substrate includes a first highly doped island that is disposed directly beneath the second device terminal and extends to the first surface of the base substrate. The first highly-doped island is laterally disposed between portions of semiconductor material having a lower net doping concentration than the first highly-doped island.Type: ApplicationFiled: March 17, 2017Publication date: September 20, 2018Inventors: Shu Yang, Giorgia Longobardi, Florin Udrea, Dario Pagnano, Gianluca Camuso, Jinming Sun, Mohamed Imam, Alain Charles