Patents by Inventor Giorgio Betti
Giorgio Betti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8867625Abstract: A method of storing a data file, particularly in the MPEG format and including a flow of different frames, comprises a protection system for the data file based on a parameter stored in the data file. Advantageously, the storage method comprises selectively protecting the frames by storing parameters that are associated with corresponding different frames whose values are selected to provide a playing quality level requested by an end user. Also, a method is provided for decoding a data file, particularly of the MPEG type and including a flow of different frames, wherein the data file is stored per above.Type: GrantFiled: November 9, 2007Date of Patent: October 21, 2014Assignee: STMicroelectronics S.r.l.Inventors: Giorgio Betti, Angelo Dati, Viviana D'Alto, Danilo Pau, Filippo Santinello
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Publication number: 20080063375Abstract: A method of storing a data file, particularly in the MPEG format and including a flow of different frames, comprises a protection system for the data file based on a parameter stored in the data file. Advantageously, the storage method comprises selectively protecting the frames by storing parameters that are associated with corresponding different frames whose values are selected to provide a playing quality level requested by an end user. Also, a method is provided for decoding a data file, particularly of the MPEG type and including a flow of different frames, wherein the data file is stored per above.Type: ApplicationFiled: November 9, 2007Publication date: March 13, 2008Inventors: Giorgio Betti, Angelo Dati, Viviana D'Alto, Danilo Pau, Filippo Santinello
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Patent number: 7295764Abstract: A method of storing a data file, particularly in the MPEG format and including a flow of different frames, comprises a protection system for the data file based on a parameter stored in the data file. Advantageously, the storage method comprises selectively protecting the frames by storing parameters that are associated with corresponding different frames whose values are selected to provide a playing quality level requested by an end user. Also, a method is provided for decoding a data file, particularly of the MPEG type and including a flow of different frames, wherein the data file is stored per above.Type: GrantFiled: June 20, 2002Date of Patent: November 13, 2007Assignee: SIMicroelectronics S.r.l.Inventors: Giorgio Betti, Angelo Dati, Viviana D'Alto, Danilo Pau, Filippo Santinello
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Patent number: 7024447Abstract: A finite impulse response (FIR) filter for implementing a Hilbert transform is provided. The FIR filter includes a plurality of programmable delay cells connected in cascade between an input terminal of the FIR filter and an output terminal of the FIR filter. Each programmable delay cell has associated therewith a constant filter coefficient and a programmable delay coefficient. The FIR filter is also applicable for processing signals originated by the reading of data from a magnetic storage media which employs perpendicular recording.Type: GrantFiled: February 27, 2001Date of Patent: April 4, 2006Assignee: STMicroelectronics S.r.l.Inventors: Valerio Pisati, Augusto Rossi, Giorgio Betti, Marco Cazzaniga
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Patent number: 6981201Abstract: A system for decoding digital signals subjected to block coding includes a post-processor that corrects the codewords affected by error, identifying them with the most likely sequence that is a channel sequence and that satisfies a syndrome check. The post-processor is a finite-state machine described by a graph that represents the set of error events. The post-processor evolves in steps through subsequent transition matrices, deleting at each step the paths that accumulate an invalid number of error events or an excessive number of wrong bits, paths that accumulate a total reliability higher than a given threshold, paths with an invalid check on the received sequence, and paths that reveal an invalid syndrome after having reached a maximum number of events.Type: GrantFiled: September 18, 2002Date of Patent: December 27, 2005Assignee: STMicroelectronics S.R.L.Inventors: Luca Reggiani, Giorgio Betti, Filippo Brenna, Angelo Dati, Davide Giovenzana, Augusto Rossi
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Patent number: 6842062Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as an inductor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.Type: GrantFiled: August 9, 2002Date of Patent: January 11, 2005Assignees: STMicroelectronics S.r.l., International Business Machines CorporationInventors: Maurizio Zuffada, Giorgio Betti, Francesco Chrappan Soldavini, Martin Aureliano Hassner
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Patent number: 6777998Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as a capacitor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.Type: GrantFiled: August 9, 2002Date of Patent: August 17, 2004Assignees: STMicroelectronics S.r.l., International Business Machines CorporationInventors: Maurizio Zuffada, Giorgio Betti, Francesco Chrappan Soldavini, Martin Aureliano Hassner
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Publication number: 20030101410Abstract: A method and apparatus for detecting and correcting errors in a magnetic recording channel of a mass storage system that combines a Soft Output Viterbi Algorithm SOVA, which has the capability of detecting the reliability of a discrete, equalized signal, and a post processor, which has the capability of detecting specific error events in said discrete, equalized signal, so as to correct error events and to generate an output bit stream.Type: ApplicationFiled: June 21, 2002Publication date: May 29, 2003Applicant: STMicroelectronics S.r.IInventors: Giorgio Betti, Filippo Brenna, Angelo Dati, Augusto Rossi, Luca Reggiani
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Publication number: 20030066021Abstract: A system For decoding digital signals subjected to block coding comprising a post-processor which corrects the codewords affected by error, identifying them with the most likely sequence which is a channel sequence and which satisfies a syndrome check. The post-processor is a finite-state machine described by a graph which represents the set of error events, the set of respective transitions defining the structure of said set of error events. Preferably, the post-processor evolves in steps through subsequent transition matrices, deleting at each step the paths which accumulate an invalid number of error events or an excessive number of wrong bits, paths which accumulate a total reliability higher than a given threshold, paths with a invalid check on the received sequence, and paths which reveal an invalid syndrome after having reached a maximum number of events.Type: ApplicationFiled: September 18, 2002Publication date: April 3, 2003Inventors: Luca Reggiani, Giorgio Betti, Filippo Brenna, Angelo Dati, Davide Giovenzana, Augusto Rossi
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Publication number: 20030058025Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as an inductor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.Type: ApplicationFiled: August 9, 2002Publication date: March 27, 2003Applicant: STMicroelectronics S.r.l.Inventors: Maurizio Zuffada, Giorgio Betti, Francesco Chrappan Soldavini, Martin Aureliano Hassner
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Publication number: 20030058024Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as a capacitor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.Type: ApplicationFiled: August 9, 2002Publication date: March 27, 2003Applicant: STMicroelectronics S.r.I.Inventors: Maurizio Zuffada, Giorgio Betti, Francesco Chrappan Soldavini, Martin Aureliano Hassner
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Publication number: 20030026596Abstract: A method of storing a data file, particularly in the MPEG format and including a flow of different frames, comprises a protection system for the data file based on a parameter stored in the data file. Advantageously, the storage method comprises selectively protecting the frames by storing parameters that are associated with corresponding different frames whose values are selected to provide a playing quality level requested by an end user. Also, a method is provided for decoding a data file, particularly of the MPEG type and including a flow of different frames, wherein the data file is stored per above.Type: ApplicationFiled: June 20, 2002Publication date: February 6, 2003Applicant: STMicroelectronics S.r.I.Inventors: Giorgio Betti, Angelo Dati, Viviana D'Alto, Danilo Pau, Filippo Santinello
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Publication number: 20010037353Abstract: A finite impulse response (FIR) filter for implementing a Hilbert transform is provided. The FIR filter includes a plurality of programmable delay cells connected in cascade between an input terminal of the FIR filter and an output terminal of the FIR filter. Each programmable delay cell has associated therewith a constant filter coefficient and a programmable delay coefficient. The FIR filter is also applicable for processing signals originated by the reading of data from a magnetic storage media which employs perpendicular recording.Type: ApplicationFiled: February 27, 2001Publication date: November 1, 2001Applicant: STMicroelectronics S.r.l.Inventors: Valerio Pisati, Augusto Rossi, Giorgio Betti, Marco Cazzaniga
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Patent number: 5623220Abstract: A zero-crossing circuit and method, in which the sign of inputs to a comparator is reversed after each zero crossing of the input signal. This means that delay introduced by the comparator does not affect the duty cycle of the output signal, so precision synchronization remains possible.Type: GrantFiled: September 13, 1994Date of Patent: April 22, 1997Assignee: SGS-Thomson Microelectonics, S.r.l.Inventors: Giorgio Betti, Paolo Gadducci, David Moloney
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Patent number: 5570380Abstract: A survival sequence register for a read channel employing a variable threshold peak qualification technique, has a first data shift register receiving a logic sum stream of two serial streams of coded digital data, corresponding to qualified peaks detected by a reading pick-up of positive and negative sign, respectively, and a pointer register. A control circuit generates an erase signal when an incoming pulse is recognized as corresponding to a detected peak of the same sign of the previously detected peak. The erase signal is input to logic gates which each drive a reset terminal of a flip-flop of the data shift register, with the exception of the first flip-flop of the register. The pointer register being reset when the control circuit receives a pulse corresponding to a peak of opposite polarity of the detected peak relative to the preceding pulse.Type: GrantFiled: November 29, 1994Date of Patent: October 29, 1996Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Paolo Gadducci, David Moloney, Giorgio Betti
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Patent number: 5528237Abstract: A decoder for decoding a serial data stream employs an extracted base clock signal, synchronous with an input, coded, serial data stream, a first fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary frequency clock signal for synthesizing a pre-decoded value, produced by a first combinative logic network, within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop. In a decoder according to the present invention, a pipelined operation is implemented by momentarily storing the bits (part of the bits handled by the decoder) that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock signal the processing, by said first combinative network, of the total n-number of bits handled by the decoder.Type: GrantFiled: August 3, 1994Date of Patent: June 18, 1996Assignee: SGS-Thomson Microelectronics, SRLInventors: David Moloney, Paolo Gadducci, Giorgio Betti, Roberto Alini
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Patent number: 5418494Abstract: A variable gain amplifier which includes a first voltage-to-current amplifier having a fixed gain; a second voltage-to-current amplifier having a variable gain, functioning in parallel to said first amplifier; a gain control and stabilization variable current generator; and a current-to-voltage converter. Current output signals produced by said first and second amplifiers and by said variable current generator are summed and the resulting current signal is converted to a voltage signal by said converter.Type: GrantFiled: March 31, 1994Date of Patent: May 23, 1995Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Giorgio Betti, David Moloney, Salvatore Portaluri
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Patent number: 5408436Abstract: The circuit structure comprises a series of storage units, a data bus, an address bus, a line for a reading/writing signal, a precharge logic suitable for precharging the address bus with a precharge address and a precharge sensor suitable for enabling the operation of address decoders of the storage units with a given delay with respect to the end of the precharge. The structure also comprises a flip-flop for controlling the address buses and the precharge logic as well as a delay circuit capable of producing a stop-writing signal with a delay calculated on the basis of the time necessary for the writing of a datum in a storage register of the storage units.Type: GrantFiled: November 23, 1992Date of Patent: April 18, 1995Assignee: SGS-Thomson Micorelectronics S.r.l.Inventors: David Moloney, Gianfranco Vai, Maurizio Zuffada, Giorgio Betti, Fabrizio Sacchi
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Patent number: 5365193Abstract: A circuit device for neutralizing thermal drift in a transconductor differential stage using a first circuit portion which corresponds structurally to the transconductor differential stage and has a pair of MOS input transistors defining a transconductance value which is substantially proportional to that of the transconductor differential stage, a pair of bipolar output transistors coupled to the MOS input transistors in a cascode configuration, and a second circuit portion being supplied a current from an output of the first differential portion to thereby output a current to be passed to the transconductor differential stage. The value of the output current is inversely proportional to temperature-dependent parameters of the transconductance.Type: GrantFiled: November 25, 1992Date of Patent: November 15, 1994Assignee: SGS-Thomson Microelectronics s.r.l.Inventors: Maurizio Zuffada, Gianfranco Vai, Marco Gregori, David Moloney, Giorgio Betti
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Patent number: RE36508Abstract: A method of automatically measuring the horizontal scan frequency of a composite synchronism signal, comprising horizontal synchronization impulses at line frequency, consists of first performing a count of a number of impulses having a repeat frequency higher than said line frequency, as intervening between two successive impulses at line frequency.The count value, corresponding to said number of impulses, is stored to obtain the line frequency of the signal, and thereafter, a series of down counts is effected, as initiated at predetermined times, until a change of frequency of the signal is detected.Type: GrantFiled: September 17, 1997Date of Patent: January 18, 2000Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Silvano Gornati, Giorgio Betti, Fabrizio Sacchi, Gianfranco Vai, Maurizio Zuffada