Abstract: The control unit is arranged to handle the requests for transmission and reception interrupts (i.e. requests to the central logic unit CPU to halt its operative program in order to transmit or receive messages to or from a peripheral unit) in arrival from the input/output interface circuits, each of which is associated with a peripheral unit. To this purpose, the interface circuits are cyclically scanned to groups of n: the presence of at least one interrupt request halts the scanning and causes a request criterion to be transmitted to the central logic unit (CPU) by the control unit. The address of the peripheral unit presenting the highest priority among those of the group requiring an interrupt is written into the state register of the control unit, the address being composed of the number of the group (supplied by the scanner) and by the code generated by a priority coder.

Abstract: A piece of luggage is disclosed which consists of a case in the shape of a flat parallelepiped comprising two greater rigid lateral walls and a rigid quadrangular frame with an upper side provided with a curved handle, a base side and end sides. At least one of its lateral walls is movable, being provided with a rigid perimetral edge which slides telescopically within the frame. Displacement of this lateral wall occurs in a direction perpendicular to its plane between a retracted position in which it is located in the plane of the corresponding edge of the frame and a projecting position. The result is that the internal volume of the case is increased.

Abstract: Two identical processors of a communication system, operating in master-slave relationship, each have a mass memory, a working memory, a CPU and an interface interlinked by an internal bus, the two interfaces being interconnected by an interprocessor bus serving for the exchange of data therebetween. When the mass memory of the slave process or needs updating, data words to be transferred from the mass memory of the master processor are fed via the interprocessor bus and a buffer store of the slave processor to the working memory thereof from which they are subsequently delivered to the associated mass memory while the CPU of the master processor performs other operations. A block of data words thus transferred is preceded by a header, emitted by the master CPU, which sets a word counter in the associated interface whose progressive decrementation determines the end of the transfer operation.

Abstract: A plurality of switching modules, e.g. components of a digital telephone exchange, each include a pair of central processing units (CPUs) operating in master-slave relationship under the supervisory control of two support processors alos constituting a master-slave pair. Each support processor communicates via a respective bus with all switching modules by way of respective signal lines extending from that bus to one CPU of each pair. Each signal line includes two closely juxtaposed, cascaded interfaces each of which, in turn, has an externally and an internally accessible input/output (I/O) section. The externally accessible I/O section of each interface inserted in the active line between the master processor and the master CPU of any module is normally operational and communicates by an in-line link with the corresponding I/O section of the interface in cascade therewith.