Abstract: A device for detecting load impedance having an analog circuit portion for detecting the impedance value of a load, and a digital circuit portion adapted to provide load impedance type information. The analog circuit portion having two power MOS transistors connected in series to each other and between a supply voltage and the ground, and a pair of mirror MOS transistors common-connected with their respective gate terminals to the gate terminals of the power MOS transistors. The digital circuit portion includes a first comparitor to determine whether the output current of an audio amplifier is higher or lower than a threshold value and a second comparator to determine whether the output voltage of the amplifier is higher than a threshold voltage, a memory to store output signals of the first and second comparitors, and a logic circuit arranged in cascade with the memory to output a load-type indication signal.

Abstract: A device for detecting load impedance having an analog circuit portion for detecting the impedance value of a load, and a digital circuit portion adapted to provide load impedance type information. The analog circuit portion having two power MOS transistors connected in series to each other and between a supply voltage and the ground, and a pair of mirror MOS transistors common-connected with their respective gate terminals to the gate terminals of the power MOS transistors. The digital circuit portion includes a first comparitor to determine whether the output current of an audio amplifier is higher or lower than a threshold value and a second comparitor to determine whether the output voltage of the amplifier is higher than a threshold voltage, a memory to store output signals of the first and second comparitors, and a logic circuit arranged in cascade with the memory to output a load-type indication signal.

Abstract: A device for detecting load impedance having an analog circuit portion for detecting the impedance value of a load, and a digital circuit portion adapted to provide load impedance type information. The analog circuit portion having two power MOS transistors connected in series to each other and between a supply voltage and the ground, and a pair of mirror MOS transistors common-connected with their respective gate terminals to the gate terminals of the power MOS transistors. The digital circuit portion includes a first comparitor to determine whether the output current of an audio amplifier is higher or lower than a threshold value and a second comparitor to determine whether the output voltage of the amplifier is higher than a threshold voltage, a memory to store output signals of the first and second comparitors, and a logic circuit arranged in cascade with the memory to output a load-type indication signal.

Abstract: The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the VDMOS transistor, and its drain region connected to the p-type junction-isolation region. The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.

Abstract: The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the VDMOS transistor, and its drain region connected to the p-type junction-isolation region. The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.

Abstract: A short-circuit protection circuit, particularly for power transistors, contains a first circuit for mirroring the output current of a power transistor which is parallel-connected to the power transistor, and a second mirroring circuit which is series-connected to the first mirroring means and is adapted to emit a current which is correlated to the current mirrored by the first mirroring circuit, for comparison with a reference current. The result of the comparison determines the need to intervene or not on the power transistor. The short-circuit protection circuit may also contain a circuit for sensing the voltage drop across the power transistor which is parallel-connected to the power transistor and to the first mirroring circuit, in order to adjust minimum and maximum values of the current in output from the power transistor, as a function of the voltage that is present across the transistor.

Abstract: An integrated amplifier includes a differential input stage including a first pair of bipolar junction transistors. A reference bias current generator biases the differential input stage with a reference bias current. A first and a second current mirror circuit drives a respective transistor of the first pair of bipolar junction transistors. Each of the first and second current mirror circuits includes a transistor having a base terminal connected to an intermediate node. An integrated resistor is connected to the intermediate node and is in series with the respective transistor of the first pair of bipolar junction transistors. The reference bias current of the differential input stage conducts through the integrated resistor. The reference bias current corresponds to a ratio between a base emitter junction voltage and a resistance of the integrated resistor.

Abstract: A CMOS output stage for providing stable quiescent current. The output stage includes a circuit that relates the quiescent current to the channel geometry of a power NMOS transistor and of an NMOS reference transistor of a reference current source. This configuration removes the dependency of the quiescent current on a power PMOS transistor used in the CMOS output stage, the threshold voltage of which may drift over time under high current and voltage operation, and adversely affects quiescent current stability.

Abstract: An integrated structure is made in a chip of semiconductor material inside an insulated N type region extending from a surface of the chip. The structure comprises a Zener diode formed by a P type first region extending from the surface inside the insulated region and by a second region of type N extending from the surface inside the first region. These regions form between themselves a buried junction, in which the structure further includes a lateral bipolar transistor having an emitter region provided by the first region.

Abstract: A power stage for an operational amplifier includes an output stage, a current source stage, and a gain stage. The output stage is formed by first and second NPN output transistors arranged in a Totem-Pole configuration, each having respective resistors connected between their respective base and emitter terminals. The output transistors are biased in class AB by a quiescent current supplied by the current source stage and are controlled dynamically by the gain stage. The gain stage includes an NPN gain transistor having a collector terminal connected to the base terminal of the first output transistor and an emitter terminal connected to the base terminal of the second output transistor.

Abstract: A sensor of instantaneous power which is dissipated through a power transistor of the MOS type connected between the output terminal of a power stage and ground. It comprises a MOS transistor having its gate terminal connected to that of the power transistor, source terminal connected to ground, and drain terminal connected to a circuit node which is coupled to the output terminal by means of a current mirror circuit which includes a resistive element in its input leg. Connected to the circuit node is the base terminal of a bipolar transistor which is respectively connected, through a diode and a constant current generator between the output terminal and ground.

Abstract: A low frequency amplifier comprising, in series, a first input stage, an intermediate amplifying stage and a final stage. The intermediate amplifying stage comprises a capacitor which is discharged when the amplifier is disabled, and is charged to a predetermined bias value when the amplifier is operative. To prevent voltage peaks at the output of the amplifier during the transient interval between the disabled and operating condition of the amplifier, a second input stage is provided which is only turned on during the transient interval, and is connected to the capacitor to detect its voltage and charge it. During the transient interval, the final stage is disabled. Upon the capacitor reaching the predetermined charge value, the second input stage practically turns itself off, and is then disabled; and, at the same time, the first input stage and the final stage are enabled to turn on the amplifier.

Abstract: An AB class stage is described which comprises two complementary MOSFET final transistors connected in a push-pull manner between two supply terminals. In order to attain high linearity, low switching distortion, a high ratio between the maximum output current and the rest current, independence of the rest current from the temperature and manufacturing variables and a circuit simplicity, the circuits determining the rest current and those which provide current to the load are substantially independent of one another. More particularly, two transconductance amplifiers are provided which control the final transistors and are dimensioned so as to have zero output current in rest conditions, two voltage generators which determine the rest current and two resistors being connected between the gate electrodes of the final transistors and the supply terminals.

Abstract: A circuit for dividing a reference current is composed of a number n of transistors connected in cascade, in a Darlington configuration, between current generator and a fractionary current output node and by N+k (where k is an integer different from zero) directly biased diodes in series, connected between the generator and the fractionary current output node. The circuit does not employ current mirrors, so all transistors may have the minimum size, which also minimizes the effects of leakage currents. Additionally, compensation elements may be used for compensating the leakage currents from the base regions of the transistors. The circuit is useful as a capacitance multiplier, or as a slow ramp generator in a large number of design situations. Independence from intrinsic parameters of the transistors used and/or from temperature of operation may be provided by employing a specifically designed reference current generator. Several embodiments are described.