Abstract: The phase of digital signals is aligned to simplify their acquisition in synchronous systems, by means of a process comprising the following steps: to apply a pulse-width distortion to the incoming signal; to sample in a uniform way such a distorted signal with a frequency which is twice than the clock frequency; to process the obtained samples, in order to re-build the bits which were present on the incoming signal; and to introduce the so obtained bits in a buffer memory, in order to re-build the original signal, now phase-aligned. The process can be carried out by means of a device with electronic circuitry that comprises: a pulse width distortion unit (DS), a unit (CF), that analyzes and samples the distorted samples, a unit (MS) which analyzes the sequences, and a phase-shift register (BF).

Abstract: Provided is a protection circuit for high speed signal communication via a two-wire connection between the two output terminals of a PECL driver and the two input terminals of a PECL receiver. The PECL driver and receiver are supplied with power from individual power supplies. The protection circuit includes two diodes connected in series with a respective wire with their cathodes electrically coupled to the respective output terminal of the PECL driver and their anodes electrically coupled to the respective input terminal of the PECL receiver, and two resistors connected between the PECL receiver power supply and the anodes of the respective diode. The resistance of the resistors ensures forward biasing of the diodes when the receiver power supply is supplying power. A capacitor may be connected in parallel with the respective diodes.