Patents by Inventor Giorgio G. Via

Giorgio G. Via has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5258264
    Abstract: A process and structure for depositing metal lines in a lift-off process is disclosed. The process comprises the deposition of a four-layer structure or lift-off stencil, comprising a first layer of a lift-off polymer etchable in oxygen plasma, a first barrier layer of hexamethyldisilizane (HMDS) resistant to an oxygenplasma, a second lift-off layer and a second barrier layer. Once these layers are deposited, a layer of photoresist is deposited and lithographically defined with the metal conductor pattern desired. The layers are then sequentially etched with oxygen and CF.sub.4, resulting in a dual overhang lift-off structure. Metal is then deposited by evaporation or sputtering through the lift-off structure. Following metal deposition, the stencil is lifted-off in a solvent such as N-methylpyrroldone (NMP).
    Type: Grant
    Filed: August 6, 1992
    Date of Patent: November 2, 1993
    Assignee: International Business Machines Corporation
    Inventors: Gangadhara S. Mathad, David Stanasolovich, Giorgio G. Via
  • Patent number: 5087537
    Abstract: An apparatus and method for characterizing lithography imaging to quickly optimize a lithography process is described. The apparatus consists of two lithography masks for use with an optical stepper, ion-beam or x-ray lithography tool. The first mask is used for creating topography on the wafer substrate, and is patterned with groups of large elements arranged in orthogonal and angular directions. The second mask is used for defining a periodic pattern over the large elements. Preferably, the periodic pattern is in the same order of dimension as the critical element on the integrated circuit. A method is provided for characterizing lithography tools which do not have lithography masks such as an electron beam exposure tool.
    Type: Grant
    Filed: October 11, 1989
    Date of Patent: February 11, 1992
    Assignee: International Business Machines Corporation
    Inventors: John F. Conway, Edward C. Fredericks, Giorgio G. Via
  • Patent number: 5024896
    Abstract: A process and structure for depositing metal lines in a lift-off process is disclosed. The process comprises the deposition of a four-layer structure or lift-off stencil, comprising a first layer of a lift-off polymer etchable in oxygen plasma, a first barrier layer of hexamethyldisilizane (HMDS) resistant to an oxygen plasma, a second lift-off layer and a second barrier layer. Once these layers are deposited, a layer of photoresist is deposited and lithographically defined with the metal conductor pattern desired. The layers are then sequentially etched with oxygen and CF.sub.4, resulting in a dual overhang lift-off structure. Metal is then deposited by evaporation or sputtering through the lift-off structure. Following metal deposition, the stencil is lifted-off in a solvent such as N-methylpyrrolidone (NMP).
    Type: Grant
    Filed: July 6, 1989
    Date of Patent: June 18, 1991
    Assignee: International Business Machines Corporation
    Inventors: Gangadhara S. Mathad, David Stanasolovich, Giorgio G. Via
  • Patent number: 4745045
    Abstract: A method which provides for a permanent planarization layer on a multilayer integrated circuit. The planarization layer resides above other circuit layers which reflect incident light. A layer of photoresist is formed over the planarization layers and imaged through a mask with circuit defining structure. During exposure of the photoresist, incident light passes through the planarization layer. Scattering from the boundary of the planarization layer and photoresist is minimized because the index of refraction of the planarization layer is substantially equal to the index of refraction of the photoresist. Light reflected from the underlaying layers is substantially absorbed by the planarization layer. Reduction of the reflected and scattered light results in improved resolution of developed images in photoresist.
    Type: Grant
    Filed: November 10, 1986
    Date of Patent: May 17, 1988
    Assignee: International Business Machines Corporation
    Inventors: Edward C. Fredericks, Giorgio G. Via
  • Patent number: 4567132
    Abstract: A photoresist photolithographic process is disclosed which provides for a single development step to develop a dual layer photoresist for lift-off, reactive ion etching, or ion implantation processes requiring a precise aperture size at the top of the photoresist layer.The process involves the deposition of two compositionally similar layers, with the first layer having the characteristic of being soluble in a developer after exposure to light and baking, and the second layer having the characteristic of being insoluble in the same developer after having been exposed to light and baked. With these two distinct characteristics for the two layers of photoresist, the effective aperture for windows in the composite photoresist can be tightly controlled in its cross-sectional dimension in the face of large variations in the developer concentration and development time.
    Type: Grant
    Filed: March 16, 1984
    Date of Patent: January 28, 1986
    Assignee: International Business Machines Corporation
    Inventors: Edward C. Fredericks, Herbert L. Greenhaus, Madan M. Nanda, Giorgio G. Via