Abstract: Methods, systems, and devices for differential storage in memory arrays are described. A memory device may include pairs of memory cells configured to store a single logic state (e.g., a single bit of information). Additionally, the memory device may include sense amplifiers configured to sense the logic state based on a difference between a voltage of a first ferroelectric memory cell of the pair of memory cells and a voltage of a second ferroelectric memory cell of the pair of memory cells. In one example, the memory device may include pairs of memory cells within a single memory array on a single level. Here, each memory cell pair may include a memory cells that are each coupled with a same word line and plate line. Additionally, each memory cell pair may include memory cells each coupled with different digit lines.

Abstract: Some embodiments include an integrated assembly having a first bottom electrode adjacent to a second bottom electrode. An intervening region is directly between the first and second bottom electrodes. Capacitor-insulative-material is adjacent to the first and second bottom electrodes. The capacitor-insulative-material is substantially not within the intervening region. Top-electrode-material is adjacent to the capacitor-insulative-material. Some embodiments include methods of forming integrated assemblies.

Abstract: A receiver includes a filter capable of receiving an input signal and generating an output signal. The filter provides a transfer function. The filter includes a first stage capable of adjusting a pole and a first zero of the transfer function. The filter also includes a second stage capable of adjusting a second zero of the transfer function. In addition, the filter includes a third stage capable of adjusting a third zero of the transfer function.

Abstract: A method includes generating an output signal at a transmitter using an input signal. The method also includes providing the output signal for communication over a communication link. The method further includes identifying a return signal by at least partially removing from the output signal at least one of: the communicated signal and base line wander. In addition, the method includes establishing a synthesized impedance to the return signal.

Abstract: A low power circuit and method for detects in-situ failures or precursors to failures in solder-joint networks on actual operational devices and packages in the field. An amplifying detector such as provided by a common-gate transistor sources current to the network to generate a signal voltage and a reference voltage that is sensitive to the low voltage applied to the other side of the network. Generation of this self-adjusting reference voltage makes the detection circuit insensitive to the network low-voltage. Additional power savings and performance gains can be provided with the addition of a differential amplifier to set a fixed bias point and a level shifter to cancel noise. The detected failure or precursor of a selected monitor solder-joint network(s) is an indicator of the integrity of other operational solder-joint networks in the package, on the PWB or between PWBs.

Abstract: A method includes generating an output signal at a transmitter using an input signal. The method also includes providing the output signal for communication over a communication link. The method further includes identifying a return signal by at least partially removing from the output signal at least one of: the communicated signal and base line wander. In addition, the method includes establishing a synthesized impedance to the return signal.

Abstract: A receiver includes a filter capable of receiving an input signal and generating an output signal. The filter provides a transfer function. The filter includes a first stage capable of adjusting a pole and a first zero of the transfer function. The filter also includes a second stage capable of adjusting a second zero of the transfer function. In addition, the filter includes a third stage capable of adjusting a third zero of the transfer function.

Abstract: A stable, process independent RC time constant for precision frequency response in automatic tuning is generated using a feedback loop employing a voltage controlled resistor to force current through the output node to equal a reference current. The only terms in the expression for the time constant affected by process variations are two resistances, which are uniformly affected by any process variations to maintain proportion. The open loop transfer function for the feedback loop contains only one pole; because no phase-locked loop or other complex circuit introducing multiple poles within the feedback loop are employed, the time constant tuning filter is intrinsically stable.

Abstract: A stable, process independent RC time constant for precision frequency response in automatic tuning is generated using a feedback loop employing a voltage controlled resistor to force current through the output node to equal a reference current. The only terms in the expression for the time constant affected by process variations are two resistances, which are uniformly affected by any process variations to maintain proportion. The open loop transfer function for the feedback loop contains only one pole; because no phase-locked loop or other complex circuit introducing multiple poles within the feedback loop are employed, the time constant tuning filter is intrinsically stable.

Abstract: A folded cascade voltage gain cell is implemented in a single stage by collapsing p-channel transistor branches receiving output currents from two sets of n-channel transistor branches and producing the output voltage into a single set of branches, summing the output currents from two sets of n-channel transistor branches in a single pair of nodes. While power consumption is only slightly improved over multistage folded cascade voltage gain cells, the circuit is implemented with fewer transistors and is therefore smaller and more reliable. Moreover, because only one gain stage is employed with a smaller number of internal nodes, the circuit's operation contains a smaller number of poles, and bandwidth is improved.

Abstract: A number of voltage-controlled resistance cells, each formed by a transistor with a biasing capacitor connected between the gate and source and an associated controller coupled to the capacitor to maintain a steady charge on the biasing capacitor and keep the gate-source voltage at a control voltage corresponding to a desired resistance, are employed to form a voltage-controlled resistance structure. The gate voltage applied to each transistor is able to “float” together with the source voltage in order to keep the gate-source voltage constant, and the resistance structure exhibits improved voltage-dependent resistance linearity together with a larger range of biasing while lowering needed refresh frequencies to avoid noise injection.

Abstract: An electroluminescent lamp is driven by a driving circuit that can supply an approximately sinusoidal signal, a bi-directional sawtooth signal or a single-ended sawtooth signal. Switches selectively transfer energy from a battery to an inductor and then from the inductor to the lamp. In one embodiment, the lamp voltage is compared to a reference waveform, such as a sinusoid. The switches are activated responsive to the error between the lamp voltage and reference waveform to minimize the error. The lamp can thus be driven with a closer approximation of the reference waveform.

Abstract: An electroluminescent lamp is driven by a driving circuit that can supply an approximately sinusoidal signal, a bi-directional sawtooth signal or a single-ended sawtooth signal. Switches selectively transfer energy from a battery to an inductor and then from the inductor to the lamp. In one embodiment, the lamp voltage is compared to a reference waveform, such as a sinusoid. The switches are activated responsive to the error between the lamp voltage and reference waveform to minimize the error. The lamp can thus be driven with a closer approximation of the reference waveform.

Abstract: A number of voltage-controlled resistance cells, each formed by a transistor with a biasing capacitor connected between the gate and source and an associated controller coupled to the capacitor to maintain a steady charge on the biasing capacitor and keep the gate-source voltage at a control voltage corresponding to a desired resistance, are employed to form a voltage-controlled resistance structure. The gate voltage applied to each transistor is able to “float” together with the source voltage in order to keep the gate-source voltage constant, and the resistance structure exhibits improved voltage-dependent resistance linearity together with a larger range of biasing while lowering needed refresh frequencies to avoid noise injection.