Abstract: An adaptive current limit circuit is provided in a power converter to achieve a fixed output current limit over duty cycle. In a converter including a high side switch, a low side switch coupled to the high side switch at a switch node, and an inductor coupled between an input voltage source and the switch node, the adaptive current limit circuit is coupled to receive the high side control signal and configured to generate an adaptive current limit threshold that varies based at least in part on the duty cycle of the high side switch.

Abstract: A method for controlling a buck-boost converter includes generating a first threshold voltage with a decreasing voltage level, generating a second threshold voltage with an increasing voltage level, and sensing an inductor current. A signal indicative of the sensed inductor current is compared to the first threshold voltage to control an on time of the high side buck switch and is compared to the second threshold voltage to control an off time of the high side boost switch. Also described is a controller including a compensator responsive to an output voltage feedback signal to generate a compensation voltage and a modulator having a buck signal path coupled to receive the compensation voltage and configured to control an on time of the high side buck switch and a boost signal path coupled to receive the compensation voltage and configured to control an off time of the high side boost switch.

Abstract: A low dropout (LDO) voltage regulator includes a first LDO stage that receives a first supply voltage and is active during a first time interval and a second LDO stage that receives a second supply voltage and is active during a second time interval. An operational amplifier receives a feedback voltage based on the LDO output voltage and provides an amplified feedback signal to the first and second LDO stages. A compensation capacitor is selectively coupled between the operational amplifier and either the first or the second LDO stage. A current limit circuit includes a sense FET coupled to the LDO pass FET, a drain voltage replication circuit coupled between the pass FET and sense FET to provide a sense current is indicative of load current when the pass FET is in a linear region, and a current comparator to compare the sense current to a predetermined current level.

Abstract: A method for controlling a buck-boost converter includes generating a first threshold voltage with a decreasing voltage level, generating a second threshold voltage with an increasing voltage level, and sensing an inductor current. A signal indicative of the sensed inductor current is compared to the first threshold voltage to control an on time of the high side buck switch and is compared to the second threshold voltage to control an off time of the high side boost switch. Also described is a controller including a compensator responsive to an output voltage feedback signal to generate a compensation voltage and a modulator having a buck signal path coupled to receive the compensation voltage and configured to control an on time of the high side buck switch and a boost signal path coupled to receive the compensation voltage and configured to control an off time of the high side boost switch.

Abstract: A low dropout (LDO) voltage regulator includes a first LDO stage that receives a first supply voltage and is active during a first time interval and a second LDO stage that receives a second supply voltage and is active during a second time interval. An operational amplifier receives a feedback voltage based on the LDO output voltage and has an output at which an amplified feedback signal is provided to both the first and second LDO stages. A compensation capacitor is selectively coupled between the operational amplifier and either the first LDO stage or the second LDO stage. A current limit circuit includes a sense FET having a gate coupled to the gate of the LDO pass FET, a drain voltage replication circuit coupled between the drains of the pass FET and sense FET to replicate the pass FET drain voltage so that the sense current is indicative of load current when the pass FET is in a linear region, and a current comparator to compare the sense current to a predetermined current level.

Abstract: A converter configured to convert a DC input voltage to a DC output voltage, may include: a high-side driver circuit having a first terminal coupled to a first die pad; a high-side transistor having a drain terminal coupled to a second die pad and a source terminal coupled to a third die pad; and a low-side transistor having a source terminal coupled to a fourth die pad and a drain terminal coupled to a fifth die pad. The converter may further include a resistive element coupled between the source terminal of the high-side transistor and the drain terminal of the low-side transistor, where a second terminal of the high-side driver circuit is coupled to a sixth die pad.

Abstract: A converter configured to convert a DC input voltage to a DC output voltage, may include: a high-side driver circuit having a first terminal coupled to a first die pad; a high-side transistor having a drain terminal coupled to a second die pad and a source terminal coupled to a third die pad; and a low-side transistor having a source terminal coupled to a fourth die pad and a drain terminal coupled to a fifth die pad. The converter may further include a resistive element coupled between the source terminal of the high-side transistor and the drain terminal of the low-side transistor, where a second terminal of the high-side driver circuit is coupled to a sixth die pad.

Abstract: Powering the internal circuitry, that is the controller of the power switch of a step-down DC-DC converter for a broad range of values of output voltage and achieving an enhanced energy saving in a low load conditions of operation is made possible by a method and implementing circuit based on defining two distinct thresholds of discrimination of the output voltage, both tied to a reference voltage, for generating two respective control signals and defining, from logical combinations of said two control signals, three distinct regions of operation of the converter upon the varying of electrical parameters, respectively identified by logical combinations of a pair of enabling signals.

Abstract: Powering the internal circuitry, that is the controller of the power switch of a step-down DC-DC converter for a broad range of values of output voltage and achieving an enhanced energy saving in a low load conditions of operation is made possible by a method and implementing circuit based on defining two distinct thresholds of discrimination of the output voltage, both tied to a reference voltage, for generating two respective control signals and defining, from logical combinations of said two control signals, three distinct regions of operation of the converter upon the varying of electrical parameters, respectively identified by logical combinations of a pair of enabling signals.

Abstract: A comparator is configured to generate an output voltage representing the comparison between the absolute value of the difference between two input voltages with an adjustable reference voltage. The comparator includes an input differential amplifier, receiving the two input voltages and connected to an active load network controlled by a control voltage, a control circuit that generates the control voltage representing the adjustable reference voltage, and an output stage having a logic circuit configured to produce the output voltage of the comparator as a logic combination of the output voltages of the differential amplifier.

Abstract: A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.

Abstract: A system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell. A first and second reference cells are coupled to the memory cell and are configured to receive a first and a second voltage. A current comparison circuit is coupled to the first and second reference cells and to the memory cell and is configured to compare current flow through the memory cell with current flow through the first and second reference cells, and to determine whether the memory cell holds a first range of values while the first reference cell receives the first voltage, and if the memory cell does not hold the first range of values, to determine whether the memory cell holds a second range of values while the second reference cell receives the second voltage, thereby reducing soft-writing during the read operation.

Abstract: A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.

Abstract: A memory device, a method for sensing a current output and a sensing circuit are disclosed. In one embodiment, a first voltage is supplied at least to a drain and a source terminal of a neighboring memory cell before sensing, and the first voltage is applied to a source terminal of a selected memory cell, while sensing the current though the selected memory cell.

Abstract: A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.

Abstract: A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.

Abstract: A fast power-on band-gap reference circuit includes a buffer, a first band-gap logic, and a second high drive band-gap logic. During power-on of the band-gap reference circuit, both the first band-gap logic and the second high drive band-gap logic are activated, in which the first band-gap logic charges an output of the first band-gap logic and the second high drive band-gap logic charges a capacitance associated with an output of the band-gap reference circuit. When the output of the first band-gap logic reaches a predetermined value, the second high drive band-gap logic is deactivated and the output of the first band-gap logic is couple to the output of the band-gap reference circuit through the buffer.

Abstract: A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.

Abstract: A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.

Abstract: A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.