Abstract: The present invention is notably directed to a photovoltaic module, or PV module, comprising an array of photovoltaic cells, or PV cells, and electrical interconnects. The array of PV cells comprises N portions, N?2, where the portions comprise, each, disjoint sets of PV cells of the array. The electrical interconnects connect the PV cells and the N portions of the array so as for PV cells within each of said portions to be electrically connected in parallel and the N portions to be connected in series. The PV cells and the portions are connected, via said interconnects, so to output an electrical current, in operation. The electrical interconnects are otherwise configured to provide electrical signals from each of the N portions. The invention is further directed to related systems and methods of fabrication and operation.

Abstract: The present invention is notably directed to a photovoltaic module, or PV module, comprising an array of photovoltaic cells, or PV cells, and electrical interconnects. The array of PV cells comprises N portions, N?2, where the portions comprise, each, disjoint sets of PV cells of the array. The electrical interconnects connect the PV cells and the N portions of the array so as for PV cells within each of said portions to be electrically connected in parallel and the N portions to be connected in series. The PV cells and the portions are connected, via said interconnects, so to output an electrical current, in operation. The electrical interconnects are otherwise configured to provide electrical signals from each of the N portions. The invention is further directed to related systems and methods of fabrication and operation.

Abstract: The present invention is notably directed to a photovoltaic module, or PV module, comprising an array of photovoltaic cells, or PV cells, and electrical interconnects. The array of PV cells comprises N portions, N?2, where the portions comprise, each, disjoint sets of PV cells of the array. The electrical interconnects connect the PV cells and the N portions of the array so as for PV cells within each of said portions to be electrically connected in parallel and the N portions to be connected in series. The PV cells and the portions are connected, via said interconnects, so to output an electrical current, in operation. The electrical interconnects are otherwise configured to provide electrical signals from each of the N portions. The invention is further directed to related systems and methods of fabrication and operation.

Abstract: The present invention is notably directed to a photovoltaic module, or PV module, comprising an array of photovoltaic cells, or PV cells, and electrical interconnects. The array of PV cells comprises N portions, N?2, where the portions comprise, each, disjoint sets of PV cells of the array. The electrical interconnects connect the PV cells and the N portions of the array so as for PV cells within each of said portions to be electrically connected in parallel and the N portions to be connected in series. The PV cells and the portions are connected, via said interconnects, so to output an electrical current, in operation. The electrical interconnects are otherwise configured to provide electrical signals from each of the N portions. The invention is further directed to related systems and methods of fabrication and operation.

Abstract: A method and apparatus for handling and positioning half plated balls for socket application in ball grid array packages. The half plated balls, comprising a first side adapted to be soldered and a second side adapted to establish reliable solderless electrical contact, are embedded in a soft foil, with a common orientation. The soft foil is positioned on a clam-receiving tool and a vacuumed caved cover clam is fitted on the balls and then pushed to cut and separate the polymer sheet from the copper ball surface. The vacuumed caved cover clam is then lifted with the oriented copper balls entrapped inside and the vacuumed caved cover clam places the entrapped balls on the laminate pads, with a deposit of low melt alloy. The air vacuum is deactivated and the cover is lifted, leaving the balls positioned on the pads while the soldering process is initiated and solder joints are formed to fix the balls.

Abstract: A coaxial via structure is adapted to transmit high speed signals or high intensity current through conductive layers of an electronic device carrier. The coaxial via structure comprises a central conductive track and an external conductive track separated by a dielectric material and is positioned in a core of the electronic device carrier or in the full thickness of the electronic device. The coaxial via structure can be combined with a stacked via structure so as allow efficient transmission of high speed signals across the electronic device carrier when a manufacturing process limits the creation of a full coaxial via structure across the entire electronic device carrier.

Abstract: A stacked via structure (200) adapted to transmit high frequency signals or high intensity current through conductive layers of an electronic device carrier is disclosed. The stacked via structure comprises at least three conductive tracks (205a, 205b, 205c) belonging to three adjacent conductive layers (110a, 110b, 110c) separated by dielectric layers (120), aligned according to z axis. Connections between these conductive tracks are done with at least two vias (210, 215) between each conductive layer. Vias connected to one side of a conductive track are disposed such that they are not aligned with the ones connected to the other side according to z axis.

Abstract: A power supply structure for high power circuit package is disclosed. According to the invention, the electrical connections between power planes are done through a plurality of coaxial structures that can be totally or partially implemented in the circuit shadow area of the electronic device carrier, for example under the engine area of the circuit. According to this principle, a same hole is used to transfer two different current levels, one on its periphery and the other one on its centre, doubling the electrical transfer capacity.

Abstract: A coaxial via structure is adapted to transmit high speed signals or high intensity current through conductive layers of an electronic device carrier. The coaxial via structure comprises a central conductive track and an external conductive track separated by a dielectric material and is positioned in a core of the electronic device carrier or in the full thickness of the electronic device. The coaxial via structure can be combined with a stacked via structure so as allow efficient transmission of high speed signals across the electronic device carrier when a manufacturing process limits the creation of a full coaxial via structure across the entire electronic device carrier.

Abstract: A method and apparatus for handling and positioning half plated balls for socket application in ball grid array packages. The half plated balls, comprising a first side adapted to be soldered and a second side adapted to establish reliable solderless electrical contact, are embedded in a soft foil, with a common orientation. The soft foil is positioned on a clam-receiving tool and a vacuumed caved cover clam is fitted on the balls and then pushed to cut and separate the polymer sheet from the copper ball surface. The vacuumed caved cover clam is then lifted with the oriented copper balls entrapped inside and the vacuumed caved cover clam places the entrapped balls on the laminate pads, with a deposit of low melt alloy. The air vacuum is deactivated and the cover is lifted, leaving the balls positioned on the pads while the soldering process is initiated and solder joints are formed to fix the balls.

Abstract: A method for partially plating balls for application in ball grid array packages is disclosed. The balls are positioned in recesses of a clam tool made of two parts, such that a gap remains between these parts. A first polymer layer is formed in this gap and one part of the clam tool is thereafter removed. The resulting exposed portions of the balls are covered with a second polymer. The second part of the clam tool is removed and the resulting second exposed portions of the balls are plated with a noble metal, such as gold or palladium. After the balls have been partially plated, the second polymer is removed, leaving the partially plated balls embedded in the first polymer layer. The first polymer layer, preferably a soft foil, may be used to position the partially plated balls for attachment to an electronic module.

Abstract: A coaxial via structure is adapted to transmit high speed signals or high intensity current through conductive layers of an electronic device carrier. The coaxial via structure comprises a central conductive track and an external conductive track separated by a dielectric material and is positioned in a core of the electronic device carrier or in the full thickness of the electronic device. The coaxial via structure can be combined with a stacked via structure so as allow efficient transmission of high speed signals across the electronic device carrier when a manufacturing process limits the creation of a full coaxial via structure across the entire electronic device carrier.

Abstract: A process for manufacturing printed wire boards with hard plated sliding contact tabs and soft plated wire bond pads. Sliding contact tabs are covered by a protective coating after being hard plated thus allowing the soft plating of wire bond pads without damaging the hard plated sliding contact tabs. In a preferred embodiment, the hard plating includes the step of electroplating nickel on the sliding contact tabs, followed by electroplating an alloy of gold and cobalt, using standard electroplating process. An electro-less soft plating process includes the steps of plating a nickel layer on the wire bond pads and then a gold layer after having “flash-etched” the copper seeding.

Abstract: A stacked via structure (200) adapted to transmit high frequency signals or high intensity current through conductive layers of an electronic device carrier is disclosed. The stacked via structure comprises at least three conductive tracks (205a, 205b, 205c) belonging to three adjacent conductive layers (110a, 110b, 110c) separated by dielectric layers (120), aligned according to z axis. Connections between these conductive tracks are done with at least two vias (210, 215) between each conductive layer. Vias connected to one side of a conductive track are disposed such that they are not aligned with the ones connected to the other side according to z axis. In a preferred embodiment, the shape of these aligned conductive tracks looks like a disk or an annular ring and four vias are used to connect two adjacent conductive layers. These four vias are symmetrically disposed on each of said conductive track.

Abstract: An optimized lid mounting for electronic device carriers, using standard manufacturing process steps of semiconductor packaging, optimizing heat dissipation and electromagnetic interference shielding is disclosed. According to the invention, conductive blocks or springs are soldered to ground pads of the chip carrier on their lower side. On the other side, these conductive blocks or springs are electrically connected to the lid with conductive adhesive material such as silicone based material. Furthermore, the lid is thermally connected to the semiconductor chip with electrical insulative adhesive material.

Abstract: A coaxial via structure adapted to transmit high speed signals or high intensity current through conductive layers of an electronic device carrier is provided. The coaxial via structure comprises a central conductive track and an external conductive track separated by a dielectric material and is positioned in a core of the electronic device carrier or in the full thickness of the electronic device. The coaxial via structure can be combined with a stacked via structure so as allow efficient transmission of high speed signals across the electronic device carrier when a manufacturing process limits the creation of a full coaxial via structure across the entire electronic device carrier.