Abstract: A system including a clock generator configured to generate a clock; a plurality of analog-to-digital converters each configured to convert a signal based on the clock, and to output a first number of bits in response to converting the signal based on the clock; and an averaging module configured to receive the first number of bits from each of the plurality of analog-to-digital converters, and to output a second number of bits. The second number of bits is greater than the first number of bits.

Abstract: A transducer for a storage medium has a supporting element positioned over the storage medium with a first head configured to interact with the storage medium and a second head operatively connected to the first head to interact with the storage medium. The second head is carried by the supporting element in a position adjacent to the first head, and the first head and the second head are aligned in a scanning direction. The first head performs the reading of a data item stored in a portion of the storage medium, the reading entailing the deletion of the data item, and the second head performs the rewriting of the data item in the same portion of the storage medium.

Abstract: In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A source-follower circuit includes a current source and a source follower output, and the source follower output is coupled to the output node. A second MOS transistor selectively couples the source-follower circuit to a second reference voltage when the output node is to be in the second state.

Abstract: A multistage analog/digital converter for converting in multi-step cycles an input signal into respective digital codes, each cycle step resolving at least one bit of a respective digital code. The converter includes: a sampling circuit inputting the signal and outputting a first sequence of analog samples; a generation block of a pseudorandom sequence of samples; a summing node, such as to input the first sequence and the pseudorandom sequence, obtaining in output a second sequence of analog samples including non-pseudorandom samples; a converter having a controllable digital gain receiving the second sequence and outputting bits of the digital codes; a feedback loop with a loop gain and including an analog amplifier; a digital calibration block to match the digital gain to the loop gain and including a prediction block to produce a digital estimation of said input signal starting from the bits resulting from converting the non-pseudorandom samples.

Abstract: In a circuit to convert a voltage range of a control signal, a first switch selectively couples, based on the control signal, an output node to a first reference voltage when the output node is to be in a first state. A second switch selectively establishes, based on the control signal, a second reference voltage when the output node is to be in a second state, the second state being a logical complement of the first state. A feedback control loop is coupled to the output node to maintain the second reference voltage in response to voltage fluctuation at the output node. The feedback control loop includes a current mirror and a transistor coupled to the current mirror. The transistor is controlled by feedback from the output node to modify a biasing current established by the current mirror to thereby counteract the voltage fluctuation.

Abstract: In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second transistor selectively discharges the output node toward a second reference voltage via a resistor when the output node is to transition from the first state to a second state, the second state being a logical complement of the first state. A source-follower circuit has a source follower output coupled to the output node and has a dynamic current source, the dynamic current source having a control input coupled to the resistor. A third transistor selectively couples the source follower output to the dynamic current source when the output node is to be in the second state.

Abstract: In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor selectively discharges the output node toward a second reference voltage when the output node is to transition from the first state to a second state, the second state a logical complement of the first state. An output of a source-follower circuit, having a current source, is coupled to the output node. A third MOS transistor selectively couples the current source of the source-follower circuit to the second reference voltage when the output node is to be in the second state.

Abstract: In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a switch selectively couples an output node to a first reference voltage when the output node is to be in a first state based on the control signal. A source-follower circuit having a current source establishes a second reference voltage. A logic circuit coupled to the switch and the source-follower circuit and having a logic gate selectively discharges, in accordance with the control signal, the output node to the second reference voltage when the output node is to transition from the first state to a second state.

Abstract: A multistage analog/digital converter for converting in multi-step cycles an input signal into respective digital codes, each cycle step resolving at least one bit of a respective digital code. The converter includes: a sampling circuit inputting the signal and outputting a first sequence of analog samples; a generation block of a pseudorandom sequence of samples; a summing node, such as to input the first sequence and the pseudorandom sequence, obtaining in output a second sequence of analog samples including non-pseudorandom samples; a converter having a controllable digital gain receiving the second sequence and outputting bits of the digital codes; a feedback loop with a loop gain and including an analog amplifier; a digital calibration block to match the digital gain to the loop gain and including a prediction block to produce a digital estimation of said input signal starting from the bits resulting from converting the non-pseudorandom samples.

Abstract: In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor has a source coupled to the output node and a gate coupled to a bias voltage. A current source circuit selectively biases the second MOS transistor to act as part of a source-follower circuit when the output node is to be in a second state. Additionally, a memory circuit has an input coupled to the output node, and an output. The memory circuit is configured to temporarily store a Boolean value of the output node when the output node transitions from the first state to the second state. Further, a discharging circuit is coupled to the output node and a second reference voltage.

Abstract: A transducer for a storage medium has a supporting element positioned over the storage medium with a first head configured to interact with the storage medium and a second head operatively connected to the first head to interact with the storage medium. The second head is carried by the supporting element in a position adjacent to the first head, and the first head and the second head are aligned in a scanning direction. The first head performs the reading of a data item stored in a portion of the storage medium, the reading entailing the deletion of the data item, and the second head performs the rewriting of the data item in the same portion of the storage medium.