Abstract: A calibration circuit may include a calibration signal generator configured to receive an oscillator signal provided by an oscillator and generate a calibration signal based on the oscillator signal. The calibration signal may be generated to have a predetermined amplitude. The calibration circuit may include a calibration peak detector configured to detect a peak amplitude of the calibration signal. The calibration circuit may include a logic circuit configured to calibrate a peak detector connected to the oscillator based at least in part on the peak amplitude of the calibration signal.

Abstract: A digital phase-locked loop (DPLL) may include a delta-sigma modulator (DSM). The DSM may include a delay component configured to perform noise shaping of a quantization error introduced by the DSM. The DSM may include a noise transfer function (NTF) component configured to perform filtering of the quantization error introduced by the DSM. The DSM may include an adjustment transfer function (ATF) component configured to cause the filtering of the quantization error to be applied on top of the noise shaping such that an impact of the NTF component on the noise shaping is reduced.

Abstract: The disclosure relates to a circuit including a current mirror circuit with a current path including a first transistor and a replica current path including a second transistor. The current path is connected to the replica current path to influence a current in the replica current path based on a reference current in the current path. The current in the replica current path may be proportional to the reference current. The circuit further includes a capacitor coupled between a gate of the second transistor and a first potential, a switch coupled between a gate of the first transistor and the gate of the second transistor to selectively disconnect the gate of the first transistor from the gate of the second transistor and from a first electrode of the capacitor. The disclosure further relates to a method for operating a circuit including a current mirror circuit.

Abstract: A calibration circuit may include a calibration signal generator configured to receive an oscillator signal provided by an oscillator and generate a calibration signal based on the oscillator signal. The calibration signal may be generated to have a predetermined amplitude. The calibration circuit may include a calibration peak detector configured to detect a peak amplitude of the calibration signal. The calibration circuit may include a logic circuit configured to calibrate a peak detector connected to the oscillator based at least in part on the peak amplitude of the calibration signal.

Abstract: A digital phase-locked loop (DPLL) may include a delta-sigma modulator (DSM). The DSM may include a delay component configured to perform noise shaping of a quantization error introduced by the DSM. The DSM may include a noise transfer function (NTF) component configured to perform filtering of the quantization error introduced by the DSM. The DSM may include an adjustment transfer function (ATF) component configured to cause the filtering of the quantization error to be applied on top of the noise shaping such that an impact of the NTF component on the noise shaping is reduced.

Abstract: A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.

Abstract: An oscillator includes: a first inductor; and a programmable capacitor bank coupled between a first terminal of the first inductor and a second terminal of the first inductor, where the programmable capacitor bank includes a plurality of cells concatenated together, where each cell of the plurality of cells includes a first node, a second node, a third node, a second inductor, and a programmable capacitor, where the second inductor is coupled between the first node and the third node, and the programmable capacitor is coupled between the third node and the second node, where a first inductance of the first inductor is larger than a sum of the inductances of the second inductors of the programmable capacitor bank.

Abstract: A method of operating a phase-locked loop (PLL) having a dynamic element matching (DEM)-driven digitally controlled oscillator (DCO) includes calibrating the PLL, where calibrating the PLL includes opening a loop of the PLL and performing linearity measurements of the DEM-driven DCO when the loop of the PLL is open and when dynamic matching of the DEM-driven DCO is activated, where performing the linearity measurements includes: applying test control words to the DEM-driven DCO to obtain frequencies in a first range of frequencies; and measuring output frequencies of the DEM-driven DCO corresponding to the test control words. Calibrating the PLL further includes calculating calibration information based on the test control words and the measured output frequencies.

Abstract: A calibration circuit for calibrating a peak detector configured to detect a signal peak amplitude of an oscillator, including: a calibration oscillator configured to be supplied by at least two different supply voltages to generate respective calibration signals; a calibration peak detector configured to detect a calibration signal peak amplitude of each of the calibration signals; and a logic circuit configured to calibrate the peak detector based on the detected calibration signal peak amplitudes.

Abstract: A calibration circuit for calibrating a peak detector configured to detect a signal peak amplitude of an oscillator, including: a calibration oscillator configured to be supplied by at least two different supply voltages to generate respective calibration signals; a calibration peak detector configured to detect a calibration signal peak amplitude of each of the calibration signals; and a logic circuit configured to calibrate the peak detector based on the detected calibration signal peak amplitudes.

Abstract: A circuit for calibrating an injection locked oscillator is provided. The injection locked oscillator includes an injection locking input, an LC tank and an oscillator output to output an oscillator output signal. The circuit is configured to adjust a capacitance of the LC tank to different values, detect an amplitude of the oscillator output signal for each value of the different values of the capacitance while an input signal having a target frequency is applied to the injection locking input, determine a maximum amplitude of the detected amplitudes, and select a value for operating the injection locked oscillator based on the determined maximum amplitude.

Abstract: A circuit for calibrating an injection locked oscillator is provided. The injection locked oscillator includes an injection locking input, an LC tank and an oscillator output to output an oscillator output signal. The circuit is configured to adjust a capacitance of the LC tank to different values, detect an amplitude of the oscillator output signal for each value of the different values of the capacitance while an input signal having a target frequency is applied to the injection locking input, determine a maximum amplitude of the detected amplitudes, and select a value for operating the injection locked oscillator based on the determined maximum amplitude.