Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.

Abstract: An interface board of a testing head for a test equipment of electronic devices is described. The testing head includes a plurality of contact probes, each contact probe having at least one contact tip suitable to abut against contact pads of a device to be tested, as well as a contact element for the connection with a board of the test equipment. Suitably, the interface board comprises a substrate and at least one redirecting die housed on a first surface of that substrate and a plurality of contact pins projecting from a second surface of that substrate opposed to the first surface. The redirecting die includes at least one semiconductor substrate whereon at least a first plurality of contact pads is realized, suitable to contact a contact element of a contact probe of the testing head, the contact pins being suitable to contact the board.

Abstract: A system and method are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores error correction information related to the blocks storing the data. The first memory and the second memory are of different types.

Abstract: A method and system are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores overhead information related to the blocks storing the data. The amount of the second memory storing the overhead information related to the at least one block of the plurality of blocks is varied.

Abstract: Embodiments for providing improved reliability or extended life for a non-volatile memory component may comprise a secondary non-volatile memory component to store error correction information, for example.

Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.

Abstract: A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating.

Abstract: An electronic system adapted to perform a corresponding function and including at least a first subsystem and a second subsystem, the first subsystem and the second subsystem being operatively couplable to each other through a plurality of electric connections to perform the function of the system, in which the first subsystem and the second subsystem are respectively integrated on a first material chip and on a second material chip, the plurality of electric connections including a plurality of conductive through holes formed in at least one of the first and second chips and adapted to form a corresponding plurality of inter-chip electric connections when the first and the second chips are superimposed.

Abstract: A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.

Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.

Abstract: A voltage regulator integrated in a chip of semiconductor material is provided.

Abstract: A non-volatile electronic memory device may be monolithically integrated on a semiconductor and be of the Flash EEPROM type having a NAND architecture and including at least one memory matrix organized in rows and columns of memory cells. Advantageously, the matrix may include at least one portion having a different data storage capacity and a different access speed than another portion.

Abstract: A method for manufacturing solder bumps for through vias in a substrate having a first surface and a second surface opposed to each other. The method includes the steps of forming a blind hole extending in the substrate from the first surface for each via and filling each blind hole with a conductive filler; a deepest part of each filler includes a bump portion made of a solder material. The method further includes the step of removing a part of the substrate extending from the second surface to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding bump.

Abstract: An integrated electronic device includes at least one supply pin and at least one booster coupled to said at least one supply pin. Moreover, there is at least one integrated circuit powered by the at least one booster and associated therewith in a “system in a package configuration.

Abstract: A level shifter is proposed.

Abstract: An embodiment of an electronic apparatus is provided. The electronic apparatus includes a supplying block for supplying a plurality of operative voltages, one or more operative circuits and a distribution bus for distributing at least part of the operative voltages to each operative circuit. Each operative circuit includes a set of devices for generating a set of output voltages from a set of input ones of the distributed operative voltages. The input and output voltages span an effective range. Each device is capable of sustaining at most a safe voltage between each pair of terminals thereof not higher than the effective range. The devices are controlled by a set of auxiliary ones of the distributed operative voltages spanning an auxiliary range within the effective range, so that a difference between the voltage applied to each pair of terminals thereof is not higher than the safe voltage.

Abstract: A circuit includes a first and a second input terminals and an output terminal. A first circuital branch is connected between the first input terminal and the output terminal, and a second circuital branch connected between the second input terminal and the output terminal. The first and second circuital branches are selectively activatable for coupling the first input terminal with the output terminal and the second input terminal with the output terminal, respectively. The first and second circuital branches each include at least one electronic device having at least a first and a second device terminals. Each electronic device can of sustain voltage differences across the first and second device terminals that are up-limited in absolute value by a first predetermined maximum value lower than the maximum of absolute values of voltage differences between the output terminal and the first input terminal, and between the output terminal and the second input terminal, respectively.

Abstract: An electronic system adapted to perform a corresponding function and including at least a first subsystem and a second subsystem, the first subsystem and the second subsystem being operatively couplable to each other through a plurality of electric connections to perform the function of the system, in which the first subsystem and the second subsystem are respectively integrated on a first material chip and on a second material chip, the plurality of electric connections including a plurality of conductive through holes formed in at least one of the first and second chips and adapted to form a corresponding plurality of inter-chip electric connections when the first and the second chips are superimposed.

Abstract: An embodiment of a non-volatile memory device is provided. The memory device includes a memory matrix comprising a plurality of memory cells, arranged according to a plurality of rows and a plurality of columns. The memory device further includes a plurality of word lines; each word line is associated with one respective row of said plurality and is connected to the memory cells of the row; the word lines are grouped into at least one packet. The memory device includes a row selector coupled to the word lines and adapted to selectively biasing them. The row selector includes, for each packet of word lines, a plurality of first paths, wherein each first path is adapted to apply a first biasing voltage to a corresponding word line of the packet depending on an operation to be performed on the memory cells connected to the corresponding word line. Each first path includes at least a first and a second selection transistors series-connected between a first terminal and a second terminal of the first path.

Abstract: A voltage regulator integrated in a chip of semiconductor material is provided.