Abstract: A tunable plasmon resonator, comprising a plasmon resonance layer made of graphene, a crystalline group-IV-semiconductor material or a crystalline group-III-V semiconductor material, and arranged on a carrier substrate, the plasmon resonance layer having a plasmon resonance region that is exposed to a sensing volume and a tuning device that is integrated into the plasmon resonator and arranged and configured to modify a density of free charge carriers in the plasmon resonance region or to modify an effective mass amount of the free charge carriers in the plasmon resonance region by applying of a control voltage to tuning control electrode(s) of the tuning device, thereby setting a plasmon frequency of plasmon polaritons in the plasmon resonance region to a desired plasmon frequency value within a plasmon frequency tuning interval, for resonance excitation of plasmon polaritons by incident electromagnetic waves of a frequency corresponding to the set plasmon frequency value.

Abstract: A semiconductor light emitter device, comprising a substrate, an active layer made of Germanium, which is configured to emit light under application of an operating voltage to the semiconductor light emitter device, wherein a gap is arranged on the substrate, which extends between two bridgeposts laterally spaced from each other, the active layer is arranged on the bridgeposts and bridges the gap, and wherein the semiconductor light emitter device comprises a stressor layer, which induces a tensile strain in the active layer above the gap.

Abstract: A tunable plasmon resonator, comprising a plasmon resonance layer made of graphene, a crystalline group-IV-semiconductor material or a crystalline group-III-V semiconductor material, and arranged on a carrier substrate, the plasmon resonance layer having a plasmon resonance region that is exposed to a sensing volume and a tuning device that is integrated into the plasmon resonator and arranged and configured to modify a density of free charge carriers in the plasmon resonance region or to modify an effective mass amount of the free charge carriers in the plasmon resonance region by applying of a control voltage to tuning control electrode(s) of the tuning device, thereby setting a plasmon frequency of plasmon polaritons in the plasmon resonance region to a desired plasmon frequency value within a plasmon frequency tuning interval, for resonance excitation of plasmon polaritons by incident electromagnetic waves of a frequency corresponding to the set plasmon frequency value.

Abstract: A semiconductor light emitter device, comprising a substrate, an active layer made of Germanium, which is configured to emit light under application of an operating voltage to the semiconductor light emitter device, wherein a gap is arranged on the substrate, which extends between two bridgeposts laterally spaced from each other, the active layer is arranged on the bridgeposts and bridges the gap, and wherein the semiconductor light emitter device comprises a stressor layer, which induces a tensile strain in the active layer above the gap.

Abstract: A method is disclosed for the cleaning of a Si surface at low temperatures. Oxide on the Si surface is brought into contact with Ge, which then sublimates off the surface. The Ge contamination remaining after the oxide removal is cleared away by an exposure to an alkali halide. The disclosed cleaning method may by used in semiconductor circuit fabrication for preparing surfaces ahead of epitaxial growth.

Abstract: A germanium on silicon waveguide photodetector disposed on a silicon on insulator (SOI) substrate. The photodetector is incorporated into a section of a planar silicon waveguide on the substrate. The photodetector generates an electric current as an infrared optical signal travels through the photodetector.

Abstract: A CMOS processing compatible germanium on silicon integrated waveguide photodiode. Positioning contacts in predicted low optical field regions, establishing side trenches in the silicon layer along the length of the photodiode reduces optical losses. Novel taper dimensions are selected based on the desirability of expected operational modes, reducing optical losses when light is injected from the silicon layer to the germanium layer. Reduced vertical mismatch systems have improved coupling between waveguide and photodiode. Light is coupled into and/or out of a novel silicon ring resonator and integrated waveguide photodiode system with reduced optical losses by careful design of the geometry of the optical path. An integrated waveguide photodiode with a reflector enables transmitted light to reflect back through the integrated waveguide photodiode, improving sensitivity. Careful selection of the dimensions of a novel integrated waveguide microdisk photodiode system results in reduced scattering.

Abstract: A germanium on silicon waveguide photodetector disposed on a silicon on insulator (SOI) substrate. The photodetector is incorporated into a section of a planar silicon waveguide on the substrate. The photodetector generates an electric current as an infrared optical signal travels through the photodetector.

Abstract: A CMOS processing compatible germanium on silicon integrated waveguide photodiode. Positioning contacts in predicted low optical field regions, establishing side trenches in the silicon layer along the length of the photodiode reduces optical losses. Novel taper dimensions are selected based on the desirability of expected operational modes, reducing optical losses when light is injected from the silicon layer to the germanium layer. Reduced vertical mismatch systems have improved coupling between waveguide and photodiode. Light is coupled into and/or out of a novel silicon ring resonator and integrated waveguide photodiode system with reduced optical losses by careful design of the geometry of the optical path. An integrated waveguide photodiode with a reflector enables transmitted light to reflect back through the integrated waveguide photodiode, improving sensitivity. Careful selection of the dimensions of a novel integrated waveguide microdisk photodiode system results in reduced scattering.

Abstract: A horizontal germanium silicon heterostructure photodetector comprising a horizontal germanium p-i-n diode disposed over a horizontal parasitic silicon p-i-n diode uses silicon contacts for electrically coupling to the germanium p-i-n through the p-type doped and n-type doped regions in the silicon p-i-n without requiring direct physical contact to germanium material. The current invention may be optically coupled to on-chip and/or off-chip optical waveguide through end-fire or evanescent coupling. In some cases, the doping of the germanium p-type doped and/or n-type doped region may be accomplished based on out-diffusion of dopants in the doped silicon material of the underlying parasitic silicon p-i-n during high temperature steps in the fabrication process such as, the germanium deposition step(s), cyclic annealing, contact annealing and/or dopant activation.

Abstract: In a computer-assisted product development system comprising a processor and a storage, a software-implemented method for asserting design rules related to the manufacturability of optoelectronic devices comprising germanium. Design rules may be established for devices comprising germanium and/or germanium and silicon heterostructures, thereby enabling and/or enhancing the manufacturability of photodetectors comprising germanium in integrated CMOS devices according to standard and/or custom CMOS processes. In some cases, design rules may be established to define allowable ranges for geometrical parameters related to the shapes defined in one or more mask layers; in some cases, design rules may be established to define allowable ranges for geometrical parameters related to the dimensions of actually constructed devices.

Abstract: The present invention discloses an integration flow of germanium into a conventional CMOS process, with improvements in performing selective area growth, and implementing electrical contacts to the germanium, in a way that has minimal impact on the preexisting transistor devices. The present invention also provides methods to integrate the germanium without impacting the optical or electrical performance of these devices, except where intended, such as in a germanium photodetector, or germanium waveguide photodetector.

Abstract: A standard CMOS process is used to fabricate optical and electronic devices at the same time on a monolithic integrated circuit. In the process, a layer of metallic salicide can be depsoited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into the core of an optical waveguide will damage the waveguide and prevent the passage of light through that section of the waveguide. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide.

Abstract: Methods for deposition of a Ge layer during a CMOS process on a monolithic device are disclosed. The insertion of the Ge layer enables the conversion of light to electrical signals easily. As a result of this method, standard metals can be attached directly to the Ge in completing an electrical circuit. Vias can also be used to connect to the Ge layer. In a first aspect of the invention, a method comprises the step of incorporating the deposition of Ge at multiple temperatures in a standard CMOS process. In a second aspect of the invention, a method comprises the step of incorporating the deposition of poly-Ge growth in a standard CMOS process.

Abstract: Methods for deposition of a Ge layer during a CMOS process on a monolithic device are disclosed. The insertion of the Ge layer enables the conversion of light to electrical signals easily. As a result of this method, standard metals can be attached directly to the Ge in completing an electrical circuit. Vias can also be used to connect to the Ge layer. In a first aspect of the invention, a method comprises the step of incorporating the deposition of Ge at multiple temperatures in a standard CMOS process. In a second aspect of the invention, a method comprises the step of incorporating the deposition of poly-Ge growth in a standard CMOS process.