Patents by Inventor Giovanni Fontana
Giovanni Fontana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11791815Abstract: A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.Type: GrantFiled: October 4, 2022Date of Patent: October 17, 2023Assignee: STMicroelectronics S.r.l.Inventors: Marco Giovanni Fontana, Marco Riva, Francesco Pulvirenti, Giuseppe Cantone
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Publication number: 20230040189Abstract: A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.Type: ApplicationFiled: October 4, 2022Publication date: February 9, 2023Applicant: STMicroelectronics S.r.l.Inventors: Marco Giovanni Fontana, Marco Riva, Francesco Pulvirenti, Giuseppe Cantone
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Patent number: 11476845Abstract: A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.Type: GrantFiled: June 22, 2021Date of Patent: October 18, 2022Assignee: STMicroelectronics S.r.l.Inventors: Marco Giovanni Fontana, Marco Riva, Francesco Pulvirenti, Giuseppe Cantone
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Publication number: 20220006450Abstract: A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.Type: ApplicationFiled: June 22, 2021Publication date: January 6, 2022Inventors: Marco Giovanni Fontana, Marco Riva, Francesco Pulvirenti, Giuseppe Cantone
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Publication number: 20210363299Abstract: The present invention relates to a process for the synthesis of partially and fully fluorinated polyether (PFPE) polymers, to PFPE polymers obtained therefrom and to the use of said PFPE polymers as intermediate compounds for the manufacture of additives for plastic and glass coating.Type: ApplicationFiled: April 18, 2019Publication date: November 25, 2021Inventors: Giovanni FONTANA, Marco GALIMBERTI, Vito TORTELLI
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Publication number: 20210246264Abstract: The present invention relates to a process for the synthesis of partially and fully fluorinated polyether (PFPE) polymers comprising cyclic moieties in the backbone chain, to PFPE polymers obtained therefrom and to the use of said PFPE polymers as intermediate compounds for the manufacture of additives for plastic and glass coating.Type: ApplicationFiled: June 19, 2019Publication date: August 12, 2021Inventors: Giovanni FONTANA, Marco GALIMBERTI, Vito TORTELLI
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Patent number: 10899883Abstract: The present invention relates to a novel process for the synthesis of (per)fluoropolyether polymers and to certain novel (per)fluoropolyether polymers. The present invention also relates to the use the (per)fluoropolyether polymers thus obtained, as intermediate compounds for the manufacture of further polymers suitable for use as lubricants, notably for magnetic recording media (MRM).Type: GrantFiled: December 12, 2017Date of Patent: January 26, 2021Assignee: SOLVAY SPECIALTY POLYMERS ITALY S.P.A.Inventors: Marco Galimberti, Giovanni Fontana, Roberto Valsecchi, Vito Tortelli
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Publication number: 20200165392Abstract: A fluorinated aromatic sulfone polymer [polymer (F-PS)] comprising: recurring units [units (A)] derived from at least one dihalo-diaryl sulfone [monomer (A)]; recurring units [units (B)] derived from at least one aromatic diol [monomer (B)]; at least one unit [units (PFPE)] derived from at least one fully or partially fluorinated polyether alcohol (PFPE alcohol), said polymer (F-PS) having a fluorine content ranging from 0.1% to 10% wt, is herein disclosed. Films and membranes obtained from (F-PS) are also disclosed, as well as their use in filtration methods.Type: ApplicationFiled: April 19, 2018Publication date: May 28, 2020Inventors: Ritu AHUJA, Trupti NALAWADE, Emanuele DI NICOLO', Giovanni FONTANA, Ivan Diego WLASSICS, Giuseppe MARCHIONNI, Claudio Adolfo Pietro TONELLI
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Publication number: 20200148820Abstract: The present invention relates to a novel process for the synthesis of (per)fluoropolyether polymers and to certain novel (per)fluoropolyether polymers. The present invention also relates to the use the (per)fluoropolyether polymers thus obtained, as intermediate compounds for the manufacture of further polymers suitable for use as lubricants, notably for magnetic recording media (MRM).Type: ApplicationFiled: December 12, 2017Publication date: May 14, 2020Inventors: Marco GALIMBERTI, Giovanni FONTANA, Roberto VALSECCHI, Vito TORTELLI
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Publication number: 20180067661Abstract: Systems and methods for intra-sector re-ordered wear leveling include: detecting, in a memory device, a high wear sub-sector having a high wear level, the sub-sector residing in a first sector; determining a second sector of the memory device having a low wear level; swapping the first sector with the second sector; and re-ordering a position of at least one sub-sector of the first sector, the second sector, or both.Type: ApplicationFiled: November 14, 2017Publication date: March 8, 2018Inventors: Marco Giovanni Fontana, Massimo Montanaro
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Patent number: 9830087Abstract: Systems and methods for intra-sector re-ordered wear leveling include: detecting, in a memory device, a high wear sub-sector having a high wear level, the sub-sector residing in a first sector; determining a second sector of the memory device having a low wear level; swapping the first sector with the second sector; and re-ordering a position of at least one sub-sector of the first sector, the second sector, or both.Type: GrantFiled: November 13, 2014Date of Patent: November 28, 2017Assignee: Micron Technology, Inc.Inventors: Marco Giovanni Fontana, Massimo Montanaro
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Patent number: 9747045Abstract: Methods of wear leveling in a memory, and memories configured to perform such methods, are useful in extending cycling endurance in memories. Such methods include transferring data from a first block of the memory to a second block of the memory, erasing the first block, transferring data from a third block of the memory to the first block, erasing the third block, transferring data from the second block to the third block, swapping logical addresses for the first block and the third block with each other, and erasing the second block. Transferring data from the third block to the first block excludes a sub-sector of the third block that is to be erased.Type: GrantFiled: November 9, 2015Date of Patent: August 29, 2017Assignee: Micron Technology, Inc.Inventors: Marco Giovanni Fontana, Massimo Montanaro, Anthony R. Cabrera, Gerald A. Kreifels
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Patent number: 9430188Abstract: A method is for operating a cryptographic device to reduce effects of power analysis and time attacks. The method may include executing a first set of cryptographic algorithm computations with a first crypto-processor of the cryptographic device. The first set of cryptographic algorithm computations may provide encryption of a first set of data to be protected with a first secret key stored in the cryptographic device. The method may further include executing a second set of cryptographic algorithm computations with a second crypto-processor of the cryptographic device for providing encryption of a second set of data different from the first set of data to be protected with a second different secret key.Type: GrantFiled: December 30, 2009Date of Patent: August 30, 2016Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Giovanni Di Sirio, Giovanni Fontana
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Publication number: 20160139826Abstract: Systems and methods for intra-sector re-ordered wear leveling include: detecting, in a memory device, a high wear sub-sector having a high wear level, the sub-sector residing in a first sector; determining a second sector of the memory device having a low wear level; swapping the first sector with the second sector; and re-ordering a position of at least one sub-sector of the first sector, the second sector, or both.Type: ApplicationFiled: November 13, 2014Publication date: May 19, 2016Inventors: Marco Giovanni Fontana, Massimo Montanaro
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Publication number: 20160062683Abstract: Methods of wear leveling in a memory, and memories configured to perform such methods, are useful in extending cycling endurance in memories. Such methods include transferring data from a first block of the memory to a second block of the memory, erasing the first block, transferring data from a third block of the memory to the first block, erasing the third block, transferring data from the second block to the third block, swapping logical addresses for the first block and the third block with each other, and erasing the second block. Transferring data from the third block to the first block excludes a sub-sector of the third block that is to be erased.Type: ApplicationFiled: November 9, 2015Publication date: March 3, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Marco Giovanni Fontana, Massimo Montanaro, Anthony R. Cabrera, Gerald A. Kreifels
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Patent number: 9275708Abstract: Decoding blocks, memories, and methods for decoding pre-decoded address information are disclosed. One such decoding block includes a first latch and voltage shift circuit configured to receive first pre-decoded address information at first voltage levels and further configured to latch the first pre-decoded address information and shift the voltage levels of the same to second voltage levels. An address decoder includes a second latch and voltage shift circuit configured to receive second pre-decoded address information at the first voltage levels and latch and shift the voltage levels of the same to the second voltage levels. The address decoder is further configured to select control gates of the memory cells of the memory based at least in part on the first and second pre-decoded address information.Type: GrantFiled: February 13, 2014Date of Patent: March 1, 2016Assignee: Micron Technology, Inc.Inventors: Marco Giovanni Fontana, Giuseppe Sciascia, Giovanni Bolognini
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Patent number: 9195590Abstract: Methods and memories for wear leveling by sub-sectors of a block are provided. In one such method, data are transferred from a first block of the memory to a second block of the memory, excluding a sub-sector of the first block that is to be erased, logical addresses for the first block and the second block are swapped with each other, the first block is erased, data are transferred from a third block to the first block, logical addresses for the first block and the third block are swapped with each other, and the third block is erased.Type: GrantFiled: August 29, 2013Date of Patent: November 24, 2015Assignee: Micron Technology, Inc.Inventors: Marco Giovanni Fontana, Massimo Montanaro, Anthony R. Cabrera, Gerald A. Kreifels
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Publication number: 20150067232Abstract: Methods and memories for wear leveling by sub-sectors of a block are provided. In one such method, data are transferred from a first block of the memory to a second block of the memory, excluding a sub-sector of the first block that is to be erased, logical addresses for the first block and the second block are swapped with each other, the first block is erased, data are transferred from a third block to the first block, logical addresses for the first block and the third block are swapped with each other, and the third block is erased.Type: ApplicationFiled: August 29, 2013Publication date: March 5, 2015Applicant: Micron Technology, Inc.Inventors: Marco Giovanni FONTANA, Massimo MONTANARO, Anthony R. CABRERA, Gerald A. KREIFELS
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Patent number: 8804949Abstract: A method for protecting data against power analysis attacks includes at least a first phase of executing a cryptographic operation for ciphering data in corresponding enciphered data through a secret key. The method includes at least a second phase of executing an additional cryptographic operation for ciphering additional data in corresponding enciphered additional data. An execution of the first and second phases is undistinguishable by the data power analysis attacks. Secret parameters are randomly generated and processed by the at least one second phase. The secret parameters include an additional secret key ERK for ciphering the additional data in the corresponding enciphered additional data.Type: GrantFiled: June 29, 2007Date of Patent: August 12, 2014Assignee: STMicroelectronics International N.V.Inventors: Giovanni Fontana, Saverio Donatiello, Giovanni Di Sirio
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Publication number: 20140160875Abstract: Decoding blocks, memories, and methods for decoding pre-decoded address information are disclosed. One such decoding block includes a first latch and voltage shift circuit configured to receive first pre-decoded address information at first voltage levels and further configured to latch the first pre-decoded address information and shift the voltage levels of the same to second voltage levels. An address decoder includes a second latch and voltage shift circuit configured to receive second pre-decoded address information at the first voltage levels and latch and shift the voltage levels of the same to the second voltage levels. The address decoder is further configured to select control gates of the memory cells of the memory based at least in part on the first and second pre-decoded address information.Type: ApplicationFiled: February 13, 2014Publication date: June 12, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Marco Giovanni Fontana, Giuseppe Sciascia, Giovanni Bolognini