Patents by Inventor Giovanni Genna

Giovanni Genna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8504326
    Abstract: Disclosed are methods and circuits for detecting and recording timestamps for multiple events (222/322, 224/324) using a single input pin (252, 352) on a real time clock (RTC) (250, 350). Signals associated with each of the events are modulated to create a multiple level composite signal (240). The RTC includes a multiple signal level detection circuit to distinguish from among the various signal levels so that each event can be separately flagged and timestamped. For example, the opening of two or more covers (112, 114) on the housing (110) of an electronic device (100) can be monitored, distinguished, and separately flagged using a single RTC input port.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: August 6, 2013
    Assignee: NXP B.V.
    Inventors: Giovanni Genna, Aleksandar Zhelyazkov, Markus Hintermann
  • Patent number: 8264801
    Abstract: Power supplies are switched in a manner that mitigates parasitic shorts. According to an example, a control circuit (e.g., 310) operates primary and backup power supplies using the higher of the primary and backup supply voltages, for switching between the power supplies.
    Type: Grant
    Filed: November 27, 2008
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventors: Friedbert Riedel, Giovanni Genna
  • Patent number: 7960864
    Abstract: Switching power supplies are implemented using a variety of methods and devices. According to an example embodiment of the present invention, an arrangement provides power to a circuit by selecting between a first supply and a second supply. The arrangement includes a first circuit that charges a first capacitive element using the first supply and generates a first reference voltage by distributing charge between the first capacitive element and a second capacitive element. The arrangement also includes a first comparator that compares the first reference voltage to a second reference voltage derived from the second supply and a second comparator that compares the first reference voltage to a third reference voltage. The arrangement further includes a power control circuit that selects one of the supplies based on the results of the comparisons.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: June 14, 2011
    Assignee: NXP B.V.
    Inventors: Friedbert Riedel, Giovanni Genna
  • Publication number: 20100301673
    Abstract: Power supplies are switched in a manner that mitigates parasitic shorts. According to an example, a control circuit (e.g., 310) operates primary and backup power supplies using the higher of the primary and backup supply voltages, for switching between the power supplies.
    Type: Application
    Filed: November 27, 2008
    Publication date: December 2, 2010
    Applicant: NXP B.V.
    Inventors: Friedbert Riedel, Giovanni Genna
  • Publication number: 20100198558
    Abstract: Disclosed are methods and circuits for detecting and recording timestamps for multiple events (222/322, 224/324) using a single input pin (252, 352) on a real time clock (RTC) (250, 350). Signals associated with each of the events are modulated to create a multiple level composite signal (240). The RTC includes a multiple signal level detection circuit to distinguish from among the various signal levels so that each event can be separately flagged and timestamped. For example, the opening of two or more covers (112, 114) on the housing (110) of an electronic device (100) can be monitored, distinguished, and separately flagged using a single RTC input port.
    Type: Application
    Filed: October 1, 2008
    Publication date: August 5, 2010
    Applicant: NXP B.V.
    Inventors: Giovanni Genna, Aleksandar Zhelyazkov, Markus Hintermann
  • Publication number: 20090322153
    Abstract: Switching power supplies are implemented using a variety of methods and devices. According to an example embodiment of the present invention, an arrangement provides power to a circuit by selecting between a first supply and a second supply. The arrangement includes a first circuit that charges a first capacitive element using the first supply and generates a first reference voltage by distributing charge between the first capacitive element and a second capacitive element. The arrangement also includes a first comparator that compares the first reference voltage to a second reference voltage derived from the second supply and a second comparator that compares the first reference voltage to a third reference voltage. The arrangement further includes a power control circuit that selects one of the supplies based on the results of the comparisons.
    Type: Application
    Filed: November 6, 2007
    Publication date: December 31, 2009
    Applicant: NXP, B.V.
    Inventors: Friedbert Riedel, Giovanni Genna
  • Patent number: 6489807
    Abstract: A method is for driving an output buffer for outputting a datum of a certain voltage level with a certain slew-rate as a function of an input datum and a first enabling signal. The first enabling signal commands the buffer to a normal functioning state or to a high impedance state. The output buffer has an output stage controlled at least by a pull-up driving circuit and a pull-down driving circuit, and an enabling circuit input with the input datum and a second enabling signal and generating control signals. The control signals may be in phase or in phase opposition depending on whether the second enabling signal is active or disabled, and they are input into the respective driving circuits.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: December 3, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giovanni Genna, Raffaele Solimene
  • Publication number: 20020105356
    Abstract: A method is for driving an output buffer for outputting a datum of a certain voltage level with a certain slew-rate as a function of an input datum and a first enabling signal. The first enabling signal commands the buffer to a normal functioning state or to a high impedance state. The output buffer has an output stage controlled at least by a pull-up driving circuit and a pull-down driving circuit, and an enabling circuit input with the input datum and a second enabling signal and generating control signals. The control signals may be in phase or in phase opposition depending on whether the second enabling signal is active or disabled, and they are input into the respective driving circuits.
    Type: Application
    Filed: August 8, 2001
    Publication date: August 8, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giovanni Genna, Raffaele Solimene