Patents by Inventor Giovanni Guaitini
Giovanni Guaitini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6687159Abstract: A method of programming a plurality of memory cells are connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier that is adapted to generate a word voltage signal, the first voltage reference being provided by a charge pump circuit. The programming method uses a program loop that includes the cells to be programmed and the operational amplifier, the charge pump circuit thus outputting a voltage ramp whose slope is a function of the cell demand. A programming circuit adapted to implement the method is also provided.Type: GrantFiled: December 19, 2001Date of Patent: February 3, 2004Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Giovanni Guaitini, Guido De Sandre, David Iezzi, Marco Poles, Pierluigi Rolandi
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Patent number: 6687167Abstract: A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.Type: GrantFiled: August 20, 2002Date of Patent: February 3, 2004Assignee: STMicroelectronics S.r.l.Inventors: Giovanni Guaitini, Marco Pasotti, Guido De Sandre, David Iezzi, Marco Poles, Pier Luigi Rolandi
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Patent number: 6655758Abstract: Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.Type: GrantFiled: December 19, 2001Date of Patent: December 2, 2003Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Guido De Sandre, Giovanni Guaitini, David Iezzi, Marco Poles, PierLuigi Rolandi
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Patent number: 6622106Abstract: A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.Type: GrantFiled: April 11, 2001Date of Patent: September 16, 2003Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Rocchi, Marco Bisio, Guido De Sandre, Giovanni Guaitini, Marco Pasotti, Pier Luigi Rolandi
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Publication number: 20030067804Abstract: The memory comprises a cell matrix, row decoder logic units, level conversion units (LSHx,y) and interface logic stages (ILOG) between the level conversion units and the row lines (WL) of the matrix. Each interface stage comprises elementary row driving stages, each with inputs (LXP, LYP) connected to the level conversion units (LSHx,y), an output connected to a row line (WL) and two supply terminals (SUPPLY_P, SUPPLY_N). Each elementary stage has an upper branch with a p-channel MOS transistor (P01) and a lower branch with an n-channel MOS transistor (N01). In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor (N00) in the upper branch and a p-channel transistor (P00) in the lower branch.Type: ApplicationFiled: August 20, 2002Publication date: April 10, 2003Inventors: Giovanni Guaitini, Marco Pasotti, Guido De Sandre, David Iezzi, Marco Poles, Pier Luigi Rolandi
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Patent number: 6535428Abstract: A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.Type: GrantFiled: June 14, 2001Date of Patent: March 18, 2003Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Guido De Sandre, Giovanni Guaitini, David Iezzi, Marco Poles, Michele Quarantelli, Pier Luigi Rolandi
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Publication number: 20020196664Abstract: A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.Type: ApplicationFiled: June 14, 2001Publication date: December 26, 2002Inventors: Marco Pasotti, Guido De Sandre, Giovanni Guaitini, David Iezzi, Marco Poles, Michele Quarantelli, Pier Luigi Rolandi
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Patent number: 6473340Abstract: A reading circuit having an array branch connected via an array bit line to an array memory cell, the content of which is to be read; a reference branch connected via a reference bit line to a current generator stage supplying a reference current; a current/voltage converter stage connected to the array branch and to the reference branch, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated to the currents flowing respectively in the array branch and in the reference branch; a comparator stage connected to the array node and the reference node for comparing the array and reference potentials; a sample and hold stage arranged between the array node and the comparator stage and selectively operable to sample and hold the array potential; and a switching off stage for switching off the array branch.Type: GrantFiled: October 27, 2000Date of Patent: October 29, 2002Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Giovanni Guaitini, Pier Luigi Rolandi, Guido De Sandre
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Patent number: 6466481Abstract: The device comprises a current mirror circuit having a first and a second node connected, respectively, to a constant current source and to a drain terminal of a memory cell to be programmed. A voltage generating circuit is connected to the first node to bias it at a constant reference voltage (VR); an operational amplifier has an inverting input connected to the first node, a non-inverting input connected to the second node, and an output connected to the control terminal of the memory cell. Thereby, the drain terminal of the memory cell is biased at the constant reference voltage, having a value sufficient for programming, and the operational amplifier and the memory cell form a negative feedback loop that supplies, on the control terminal of the memory cell, a ramp voltage (VPCX) that causes writing of the memory cell. The ramp voltage increases with the same speed as the threshold voltage and can thus be used to know when the desired threshold value is reached, and thus when programming must be stopped.Type: GrantFiled: November 12, 1999Date of Patent: October 15, 2002Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Roberto Canegallo, Giovanni Guaitini, Pier Luigi Rolandi
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Publication number: 20020118573Abstract: Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.Type: ApplicationFiled: December 19, 2001Publication date: August 29, 2002Applicant: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Guido De Sandre, Giovanni Guaitini, David Iezzi, Marco Poles, PierLuigi Rolandi
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Publication number: 20020105835Abstract: A method of programming a plurality of memory cells are connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier that is adapted to generate a word voltage signal, the first voltage reference being provided by a charge pump circuit. The programming method uses a program loop that includes the cells to be programmed and the operational amplifier, the charge pump circuit thus outputting a voltage ramp whose slope is a function of the cell demand. A programming circuit adapted to implement the method is also provided.Type: ApplicationFiled: December 19, 2001Publication date: August 8, 2002Applicant: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Giovanni Guaitini, Guido De Sandre, David Iezzi, Marco Poles, Pierluigi Rolandi
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Patent number: 6400607Abstract: A reading circuit having an array branch connected to a multi-level array memory cell; a reference branch connected to a reference memory cell; a current/voltage converter stage formed of a current mirror having a variable mirror ratio, connected to the array and reference branches, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated respectively to the currents flowing in the array branch and in the reference branch; and a comparator stage having a first and a second input connected to the array and reference nodes for comparing with one another the array and reference potentials.Type: GrantFiled: October 27, 2000Date of Patent: June 4, 2002Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Giovanni Guaitini, Pier Luigi Rolandi, Guido De Sandre
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Patent number: 6392931Abstract: A programming method comprises the steps of applying a ramp voltage having a first slope to the gate terminal of a selected memory cell to rapidly bring the threshold voltage of the selected cell to an intermediate value; then applying a ramp voltage having a second slope lower than the first, to end programming to the desired final threshold value with high precision. Thereby, when a high threshold value is to be programmed, programming time is reduced; on the other hand, if a low threshold value is to be programmed, the slower ramp voltage is applied right from the start, to prevent possible overprogramming of the cell.Type: GrantFiled: November 24, 1999Date of Patent: May 21, 2002Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Roberto Canegallo, Giovanni Guaitini, Frank Lhermet, Pier Luigi Rolandi
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Publication number: 20020036537Abstract: An electronic circuit for controlling voltage signals at particular critical nodes of an electronic device connected to the circuit, said circuit being inserted between a supply voltage reference and a ground voltage reference, and having at least one internal reference node connected to the critical nodes, and including at least one capacitive element inserted between the supply voltage reference and the ground voltage reference, and connected to the internal reference node through a charging device, said capacitive element being charged with the supply voltage reference to maintain, at the internal reference node, a voltage value above a predetermined threshold voltage as the supply voltage reference is cut off.Type: ApplicationFiled: August 1, 2001Publication date: March 28, 2002Inventors: Giovanni Guaitini, Marco Pasotti, Pier Luigi Rolandi
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Patent number: 6323799Abstract: A reading device having an A/D converter of n+m bits receiving an input signal correlated to the threshold voltage of the memory cell, and supplying a binary output word of n+m bits. The A/D converter is of a double conversion stage type, wherein a first A/D conversion stage carries out a first analog/digital conversion of the input signal to supply at the output a first intermediate binary word of n bits, and the second A/D conversion stage can be activated selectively to carry out a second analog/digital conversion of a difference signal correlated to the difference between the input signal and the value of the first intermediate binary word. The second A/D conversion stage generates at the output a second intermediate binary word of m bits that is supplied along with the first intermediate binary word to an adder, which generates the binary output word of n+m bits.Type: GrantFiled: October 19, 1999Date of Patent: November 27, 2001Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Roberto Canegallo, Giovanni Guaitini, Pier Luigi Rolandi
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Publication number: 20010044702Abstract: A digital device for testing and calibrating the oscillation frequency of an integrated oscillator, integrated in an integrated circuit of a type that includes at least one storage and control section, a plurality of connection pins connected bidirectionally to the storage and control section, and an external generator delivering a reference signal of known duration to at least a first digital input pin of the plurality of connection pins.Type: ApplicationFiled: April 11, 2001Publication date: November 22, 2001Inventors: Alessandro Rocchi, Marco Bisio, Guido De Sandre, Giovanni Guaitini, Marco Pasotti, Pier Luigi Rolandi
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Patent number: 6314043Abstract: Circuit for erasing and rewriting blocks of memory cells and particularly of analog flash cells, including at least one row decoding circuit including at least two adder blocks, suitable to generate a row address signal, at least two decoder blocks, suitable to generate respective pluralities of signals identifying a respective sector of memory to be enabled, at least two shifter blocks, suitable to generate an address signal of another row to be enabled, at least two OR logic blocks, suitable to generate respective signals serving the purpose to simultaneously enable at least two rows of the memory matrix.Type: GrantFiled: June 13, 2000Date of Patent: November 6, 2001Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Giovanni Guaitini, Pier Luigi Rolandi
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Patent number: 6292398Abstract: A method for the in-writing verification of the threshold value of the multilevel cells suitable to memorize n bits each, that provides for the utilization of a sense amplifier containing a respective successive approximation register. An output signal of a comparison circuit provides for the loading of the datum to be programmed in the cell being selected, after which a programming pulse is applied and the comparison between the reference current corresponding to said datum and the current that flows in the cell is carried out. The application of the programming pulse and the performance of the comparison are then repeated until it is verified that the current of the cell is smaller than the reference current.Type: GrantFiled: May 11, 2000Date of Patent: September 18, 2001Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Giovanni Guaitini, Pier Luigi Rolandi
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Patent number: 6282125Abstract: A method for erasing non volatile memories, in particular flash cells, that includes applying erasing pulses to the cells to be erased and to verify, after each pulse, the value of the threshold voltage of the cells. The erasing pulses are provided to the cells as long as the respective values of the threshold voltage are greater than the new values of threshold voltage corresponding to new data to be rewritten in the cells to be erased.Type: GrantFiled: April 20, 2000Date of Patent: August 28, 2001Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Giovanni Guaitini, Pier Luigi Rolandi
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Patent number: 6259626Abstract: A method for storing n bytes in multi-level non-volatile memory cells, including writing and reading of said n bytes. Writing includes the following steps: (a) decomposing each one of such n bytes into eight bits, (b) storing each one of such eight bits into a respective one of such multi-level non-volatile memory cells by utilizing a multi-level technology. Reading includes the following steps: (c) reading contemporaneously each one of such eight bits which belong to each one of said n bytes by sense amplifiers each connected to each one of such multi-level non-volatile memory cells, (d) assembling such eight bits previously read to form each one of such initial n bytes.Type: GrantFiled: July 14, 2000Date of Patent: July 10, 2001Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Giovanni Guaitini, Pier Luigi Rolandi