Patents by Inventor Giovanni Guasti
Giovanni Guasti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10832757Abstract: A receiver implemented in an integrated circuit device is described. The receiver circuit comprises a first receiver circuit configured to receive first data, wherein the first receiver circuit comprises a first memory element configured to receive the first data in response to a first clock signal; a latency mirror circuit configured to receive second data, wherein the latency mirror circuit comprises a second memory element configured to receive the second data in response to a second clock signal; and a latency control circuit configured to detect a latency in the second data, wherein the latency control circuit adjusts a phase of the first clock signal used to receive the first data in the first receiver circuit.Type: GrantFiled: February 19, 2019Date of Patent: November 10, 2020Assignee: XILINX, INC.Inventors: Paolo Novellini, Giovanni Guasti
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Patent number: 10291501Abstract: An integrated circuit (IC) includes a first device and a second device. A latency measurement circuit is configured to determine a first latency of the first device; and determine a second latency of the second device based on the first latency.Type: GrantFiled: February 1, 2018Date of Patent: May 14, 2019Assignee: XILINX, INC.Inventors: Paolo Novellini, Giovanni Guasti
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Patent number: 9331724Abstract: In a method relating generally to starting a plurality of transmitters, a sequence is initiated for each of the plurality of transmitters having corresponding data buffers. Latency is set for each of the data buffers responsive to execution of the sequence. The sequence includes: obtaining a read address associated with a read clock signal; obtaining a write address associated with a write clock signal; determining a difference between the read address and the write address; asserting a flag signal associated with the difference; and adjusting the read clock signal to change the difference to locate a change of state location for the flag signal to set the latency for a data buffer of the data buffers.Type: GrantFiled: September 15, 2014Date of Patent: May 3, 2016Assignee: XILINX, INC.Inventors: Paolo Novellini, Giovanni Guasti
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Publication number: 20160080008Abstract: In a method relating generally to starting a plurality of transmitters, a sequence is initiated for each of the plurality of transmitters having corresponding data buffers. Latency is set for each of the data buffers responsive to execution of the sequence. The sequence includes: obtaining a read address associated with a read clock signal; obtaining a write address associated with a write clock signal; determining a difference between the read address and the write address; asserting a flag signal associated with the difference; and adjusting the read clock signal to change the difference to locate a change of state location for the flag signal to set the latency for a data buffer of the data buffers.Type: ApplicationFiled: September 15, 2014Publication date: March 17, 2016Applicant: XILINX, INC.Inventors: Paolo Novellini, Giovanni Guasti
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Patent number: 8724764Abstract: A system can include a phase detector configured to generate a phase error signal indicating a phase error of an input signal compared to an output signal and a first filter coupled to the phase detector and configured to generate a first control signal derived from the phase error signal. The system can include a pattern error detector configured to generate a pattern error signal specifying a pattern error of the input signal compared to the output signal and a second filter coupled to the pattern error detector and configured to generate a second control signal derived from the pattern error signal. The system further can include a controlled oscillator coupled to the first filter and the second filter, wherein the controlled oscillator is configured to generate the output signal responsive to the first control signal, the second control signal, and a center frequency signal.Type: GrantFiled: May 30, 2012Date of Patent: May 13, 2014Assignee: Xilinx, Inc.Inventors: Giovanni Guasti, Paolo Novellini
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Publication number: 20130321047Abstract: A system can include a phase detector configured to generate a phase error signal indicating a phase error of an input signal compared to an output signal and a first filter coupled to the phase detector and configured to generate a first control signal derived from the phase error signal. The system can include a pattern error detector configured to generate a pattern error signal specifying a pattern error of the input signal compared to the output signal and a second filter coupled to the pattern error detector and configured to generate a second control signal derived from the pattern error signal. The system further can include a controlled oscillator coupled to the first filter and the second filter, wherein the controlled oscillator is configured to generate the output signal responsive to the first control signal, the second control signal, and a center frequency signal.Type: ApplicationFiled: May 30, 2012Publication date: December 5, 2013Applicant: XILINX, INC.Inventors: Giovanni Guasti, Paolo Novellini
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Patent number: 7917797Abstract: Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors.Type: GrantFiled: May 22, 2008Date of Patent: March 29, 2011Assignee: Xilinx, Inc.Inventors: Paolo Novellini, Silvio Cucchi, Giovanni Guasti
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Publication number: 20090289667Abstract: Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors.Type: ApplicationFiled: May 22, 2008Publication date: November 26, 2009Applicant: Xilinx, IncInventors: Paolo Novellini, Silvio Cucchi, Giovanni Guasti