Patents by Inventor Giovanni Naso
Giovanni Naso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9646683Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.Type: GrantFiled: July 20, 2015Date of Patent: May 9, 2017Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Tommaso Vali, Giovanni Naso, Vishal Sarin, William Henry Radke, Theodore T. Pekny
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Patent number: 9520183Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.Type: GrantFiled: May 8, 2015Date of Patent: December 13, 2016Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Tommaso Vali, Giovanni Naso, Vishal Sarin, William Henry Radke, Theodore T. Pekny
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Publication number: 20150325309Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Inventors: Violante Moschiano, Tommaso Vali, Giovanni Naso, Vishal Sarin, William Henry Radke, Theodore T. Pekny
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Publication number: 20150243351Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.Type: ApplicationFiled: May 8, 2015Publication date: August 27, 2015Inventors: Violante Moschiano, Tommaso Vali, Giovanni Naso, Vishal Sarin, William Henry Radke, Theodore T. Pekny
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Patent number: 9087594Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.Type: GrantFiled: July 31, 2012Date of Patent: July 21, 2015Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Tommaso Vali, Giovanni Naso, Vishal Sarin, William Henry Radke, Theodore T. Pekny
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Patent number: 9030870Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.Type: GrantFiled: August 26, 2011Date of Patent: May 12, 2015Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Tommaso Vali, Giovanni Naso, Vishal Sarin, William Henry Radke, Theodore T. Pekny
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Publication number: 20130058164Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.Type: ApplicationFiled: July 31, 2012Publication date: March 7, 2013Inventors: Violante Moschiano, Tommaso Vali, Giovanni Naso, Vishal Sarin, William Henry Radke, Theodore T. Pekny
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Publication number: 20130051141Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.Type: ApplicationFiled: August 26, 2011Publication date: February 28, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Tommaso Vali, Giovanni Naso, Vishal Sarin, William Henry Radke, Theodore T. Pekny
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Patent number: 8275926Abstract: In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.Type: GrantFiled: April 25, 2011Date of Patent: September 25, 2012Assignee: Micron Technology, Inc.Inventors: Giovanni Naso, Stefano Donnola
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Publication number: 20110208902Abstract: In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.Type: ApplicationFiled: April 25, 2011Publication date: August 25, 2011Inventors: Giovanni Naso, Stefano Donnola
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Patent number: 7934048Abstract: In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.Type: GrantFiled: November 16, 2009Date of Patent: April 26, 2011Assignee: Micron Technology, Inc.Inventors: Giovanni Naso, Stefano Donnola
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Patent number: 7738310Abstract: One or more embodiments of the present disclosure provide methods, devices, and systems for operating memory devices having fuse circuits. One method embodiment includes detecting a signal indicating whether a voltage used during operation of at least one of a number of fuse circuits has reached a threshold level, initializing at least one of the number of fuse circuits in response to detecting that the voltage has reached the threshold level, and reading an output of at least one of the number of fuse circuits at least partially in response to a detected state change of an output of the at least one initialized fuse circuit.Type: GrantFiled: February 18, 2008Date of Patent: June 15, 2010Assignee: Micron Technology, Inc.Inventors: Giovanni Naso, Stefano Donnola
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Publication number: 20100064188Abstract: In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.Type: ApplicationFiled: November 16, 2009Publication date: March 11, 2010Inventors: Giovanni Naso, Stefano Donnola
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Patent number: 7657802Abstract: A first series combination of bit match circuits compares a predetermined bit position in data words that are involved in a compression operation. The first series combination compares the values in the predetermined bit position to determine if they are all a logical zero. A second series combination of bit match circuits compares the same predetermined bit position in the data words. The second series combination compares the values to determine if they are all a logical one. If either condition is true, the value of the bit is output through an output buffer. If both conditions are false, the output buffer is placed in a high impedance state to indicate an error condition exists in that bit position.Type: GrantFiled: July 20, 2007Date of Patent: February 2, 2010Assignee: Micron Technology, Inc.Inventor: Giovanni Naso
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Patent number: 7635991Abstract: Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage output buffer. A user can opt for a default capacitive load, or adjust the strength by enabling one or more stages of the multiple stage output buffer.Type: GrantFiled: May 2, 2006Date of Patent: December 22, 2009Assignee: Micron Technology, Inc.Inventors: Girolamo Gallo, Giulio Marotta, Giovanni Naso
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Patent number: 7620859Abstract: In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.Type: GrantFiled: December 19, 2006Date of Patent: November 17, 2009Assignee: Micron Technology, Inc.Inventors: Giovanni Naso, Stefano Donnola
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Patent number: 7565587Abstract: Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check operations. Such apparatus and methods facilitate subsequent checks for data gain of erased memory cells using abbreviated procedures compared to normal erase operations.Type: GrantFiled: September 12, 2006Date of Patent: July 21, 2009Assignee: Micron Technology, Inc.Inventors: Giuliano Gennaro Imondi, Giovanni Naso
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Publication number: 20090067252Abstract: One or more embodiments of the present disclosure provide methods, devices, and systems for operating memory devices having fuse circuits. One method embodiment includes detecting a signal indicating whether a voltage used during operation of at least one of a number of fuse circuits has reached a threshold level, initializing at least one of the number of fuse circuits in response to detecting that the voltage has reached the threshold level, and reading an output of at least one of the number of fuse circuits at least partially in response to a detected state change of an output of the at least one initialized fuse circuit.Type: ApplicationFiled: February 18, 2008Publication date: March 12, 2009Applicant: Micron Technology, Inc.Inventors: Giovanni Naso, Stefano Donnola
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Patent number: 7434152Abstract: Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode having more than one level of compression. The time necessary to read and verify a repeating test pattern can be reduced as only a fraction of the words of the memory device need be read to determine the ability of the memory device to accurately write and store data values. Output is selectively disabled if a bit location for one word of a group of words has a data value differing from any remaining word of its group of words for a number of groups of words.Type: GrantFiled: May 12, 2005Date of Patent: October 7, 2008Assignee: Micron Technology, Inc.Inventor: Giovanni Naso
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Publication number: 20080086604Abstract: In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.Type: ApplicationFiled: December 19, 2006Publication date: April 10, 2008Inventors: Giovanni Naso, Stefano Donnola