Patents by Inventor Giovanni Santin
Giovanni Santin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10922220Abstract: Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can receive a page of data. The memory controller can segment the page of data into a group of data segments. The memory controller can program the group of data segments to memory cells in the plurality of memory cells that are associated with an inhibit tile group (ITG). The group of data segments for the page of data can be programmed using all bits included in each of the memory cells associated with the ITG.Type: GrantFiled: July 1, 2017Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: Umberto Siciliani, Giulio Giuseppe Marotta, Tommaso Vali, Luca De Santis, Agostino Macerola, Violante Moshciano, Luigi Pilolli, Giovanni Santin, Michele Incarnati
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Patent number: 10885987Abstract: A method for reading an array of memory cells includes enabling a current to flow through even data lines of the array of memory cells. The method includes blocking a current from flowing through odd data lines of the array of memory cells. The method includes sensing data stored in memory cells coupled to the even data lines.Type: GrantFiled: December 20, 2018Date of Patent: January 5, 2021Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Andrea D'Alessandro, Tommaso Vali, Giovanni Santin
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Publication number: 20200202950Abstract: A method for reading an array of memory cells includes enabling a current to flow through even data lines of the array of memory cells. The method includes blocking a current from flowing through odd data lines of the array of memory cells. The method includes sensing data stored in memory cells coupled to the even data lines.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Andrea D'Alessandro, Tommaso Vali, Giovanni Santin
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Patent number: 10671479Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).Type: GrantFiled: August 20, 2018Date of Patent: June 2, 2020Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Walter Di Francesco, Luca De Santis, Giovanni Santin
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Patent number: 10446258Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.Type: GrantFiled: October 2, 2017Date of Patent: October 15, 2019Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Giovanni Santin, Maria-Luisa Gallese, Luigi Pilolli
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Publication number: 20190018733Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).Type: ApplicationFiled: August 20, 2018Publication date: January 17, 2019Inventors: Violante Moschiano, Walter Di Francesco, Luca De Santis, Giovanni Santin
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Publication number: 20190004938Abstract: Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can receive a page of data. The memory controller can segment the page of data into a group of data segments. The memory controller can program the group of data segments to memory cells in the plurality of memory cells that are associated with an inhibit tile group (ITG). The group of data segments for the page of data can be programmed using all bits included in each of the memory cells associated with the ITG.Type: ApplicationFiled: July 1, 2017Publication date: January 3, 2019Applicant: Intel CorporationInventors: Umberto Siciliani, Giulio Giuseppe Marotta, Tommaso Vali, Luca De Santis, Agostino Macerola, Violante Moshciano, Luigi Pilolli, Giovanni Santin, Michele Incarnati
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Patent number: 10055293Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).Type: GrantFiled: May 1, 2017Date of Patent: August 21, 2018Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Walter Di Francesco, Luca De Santis, Giovanni Santin
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Patent number: 10014062Abstract: Memory devices including an array of memory cells, a first buffer selectively connected to the array of memory cells and corresponding to a particular bit rank of a byte of information of a programming operation of the memory device, and a second buffer selectively connected to the array of memory cells and corresponding to the particular bit rank of a different byte of information of the programming operation of the memory device, wherein an output of the first buffer and an output of the second buffer are connected in parallel to a common line, as well as methods of their operation to indicate a pass/fail condition of the programming operation.Type: GrantFiled: March 30, 2016Date of Patent: July 3, 2018Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Giovanni Santin
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Publication number: 20180047460Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.Type: ApplicationFiled: October 2, 2017Publication date: February 15, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Giovanni Santin, Maria-Luisa Gallese, Luigi Pilolli
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Patent number: 9779839Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data.Type: GrantFiled: November 13, 2015Date of Patent: October 3, 2017Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Giovanni Santin, Maria-Luisa Gallese, Luigi Pilolli
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Publication number: 20170235637Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).Type: ApplicationFiled: May 1, 2017Publication date: August 17, 2017Inventors: Violante Moschiano, Walter Di Francesco, Luca De Santis, Giovanni Santin
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Patent number: 9639420Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).Type: GrantFiled: March 13, 2015Date of Patent: May 2, 2017Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Walter Di Francesco, Luca De Santis, Giovanni Santin
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Patent number: 9558831Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.Type: GrantFiled: May 18, 2015Date of Patent: January 31, 2017Assignee: Micron Technology, Inc.Inventors: Paul D. Ruby, Violante Moschiano, Giovanni Santin
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Patent number: 9455043Abstract: A memory device has a controller. The controller is configured to cause the memory device to inhibit programming of a group of memory cells. The controller is configured to cause the memory device to apply a programming pulse to control gates of the group of memory cells. The controller is configured to determine an amount of disturb experienced by the group of memory cells responsive to the programming pulse. The controller is configured to determine a program window responsive to the amount of disturb.Type: GrantFiled: March 21, 2016Date of Patent: September 27, 2016Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Giovanni Santin, Massimo Rossini, William H. Radke, Violante Moschiano
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Publication number: 20160266966Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).Type: ApplicationFiled: March 13, 2015Publication date: September 15, 2016Inventors: Violante Moschiano, Walter Di Francesco, Luca De Santis, Giovanni Santin
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Publication number: 20160211034Abstract: Memory devices including an array of memory cells, a first buffer selectively connected to the array of memory cells and corresponding to a particular bit rank of a byte of information of a programming operation of the memory device, and a second buffer selectively connected to the array of memory cells and corresponding to the particular bit rank of a different byte of information of the programming operation of the memory device, wherein an output of the first buffer and an output of the second buffer are connected in parallel to a common line, as well as methods of their operation to indicate a pass/fail condition of the programming operation.Type: ApplicationFiled: March 30, 2016Publication date: July 21, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Giovanni Santin
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Publication number: 20160203875Abstract: A memory device has a controller. The controller is configured to cause the memory device to inhibit programming of a group of memory cells. The controller is configured to cause the memory device to apply a programming pulse to control gates of the group of memory cells. The controller is configured to determine an amount of disturb experienced by the group of memory cells responsive to the programming pulse. The controller is configured to determine a program window responsive to the amount of disturb.Type: ApplicationFiled: March 21, 2016Publication date: July 14, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Tommaso Vali, Giovanni Santin, Massimo Rossini, William H. Radke, Violante Moschiano
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Patent number: 9343169Abstract: Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.Type: GrantFiled: January 23, 2014Date of Patent: May 17, 2016Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Giovanni Santin, Michele Incarnati, Violante Moschiano
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Patent number: 9305659Abstract: A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programing operation performed on the memory device using the determined program window.Type: GrantFiled: August 14, 2015Date of Patent: April 5, 2016Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Giovanni Santin, Massimo Rossini, William H. Radke, Violante Moschiano