Abstract: An equalizer with two parallel branches for precursor and postcursor correction, receiving periodically incoming binary pulse samples, generates for each sample two purged symbols f, b at the outputs of these branches along with two decided symbols f and b, all of which are transmitted to a logic network checking whether or not the two decided symbols are identical. In the event of a disparity, the network produces an estimated signal s, calculates the absolute differences d.sub.sf, d.sub.sb between signals s and f, b, supplements them with further signals d.sub.f, d.sub.b representing the contributions of postcursors and precursors from one or more preceding and following samples, and compares resulting discriminatory signals D.sub.f and D.sub.b to determine which of the two decided symbols should be emitted as an output signal of the equalizer.

Abstract: An equalizer designed to correct both precursor and postcursor distortion in signal samples periodically obtained from a train of digital symbols comprises two parallel circuit branches each including a delay line preceded by a linear upstream filter for postcursor suppression in the case of the first branch and precursor suppression in the case of the second branch. A decision stage in parallel with the delay line of the first branch works into a nonlinear downstream filter delivering a precursor-correcting signal to an adder which also receives precorrected earlier signals from the two delay lines. A second decision stage connected to an output of the adder feeds back to that adder a postcursor-correction signal via another nonlinear downstream filter. The purged signal emitted by the second decision stage may be subjected to additional filtering and precursor/postcursor correction with the aid of another adder and a third decision stage provided with a further feedback loop.

Abstract: An equalizer designed to correct both precursor and postcursor distortion in signal samples periodically obtained from a digital signal train comprises two parallel, mutually complementary circuit branches each including an upstream filter for linearly correcting one type of distortion and a downstream cell for nonlinearly compensating the other type of distortion. The compensating cell of the first branch includes an adder algebraically combining a feed-forward signal with a signal at least partly freed from postcursor interference in the corresponding upstream filter; the second branch includes another adder algebraically combining a feedback signal from its compensating cell with a prefiltered signal at least partly freed from precursor interference.

Abstract: An equalization system for eliminating precursor and postcursor interference effects from an incoming train of digital pulses comprises a cascade of decision stages interleaved with correction units emitting precursor-compensation signals to immediately following digital adders for algebraic combination with the incoming digital pulse train received thereby from a cascade of delay lines, the adders feeding the resulting precursor-compensated signals to respective decision stages. Postcursor compensation may be at least partially accomplished in a Viterbi or Ungerboeck receiver forming one of the decision stages or may be performed in an equalization cell having a correction unit transmitting postcursor-compensation signals to a digital adder inserted in the cascade of delay lines for substantially eliminating postcursor interference permanently.

Abstract: To translate a train of binary electrical pulses into a multilevel luminous signal transmissible at a lower frequency, groups of two or more electrical pulses are temporarily stored in a shift register and then concurrently read out to a set of 2.sup.n -1 amplifiers feeding as many light emitters where n is the number of pulses per group. The connections between the shift-register stages and the amplifiers are so arranged that the collective intensity of the several light emitters assumes one of 2.sup.n possible levels according to the binary value of the pulse group stored in the register. The light sources jointly illuminate an optical fiber, with deviation of some of their rays to electro-optical feedback circuits for controlling the gain of the amplifiers to stabilize their output currents.

Abstract: A receiver of digital signal pulses, operating with a sampling period T, comprises an equalizer which includes at least one feedback loop from the output of a decision unit for subtracting from an incoming signal pulse a value corresponding to the magnitude of a tail or postcursor of a preceding signal pulse. The signal pulse thus purged of postcursor interference is delayed by one or more sampling periods T for algebraic combination with one or more fed-forward compensating signals each representing the estimated value of an interfering precursor sample, these compensating signals being derived from the outputs of respective decision units with the aid of filters.

Abstract: In a phase-shift-keying (PSK) signaling system with or without amplitude modulation, using two conjugate channel carriers of like frequency, the signals incoming at a receiver input over the two channels are coherently detected and filtered to supply a pair of coordinates defining a point on an orthogonal matrix divided into eight sectors, each sector representing a respective signal level. The coordinate values are quantized and translated into selective energization of two mutually orthogonal matrix leads whereby an associated AND gate conducts and emits a signal identifying the sector encompassing the intersection of these leads. The sector-identifying signal addresses a read-only memory which delivers a corresponding output signal to a processor and feeds back corrective signals to a pair of summing circuits for superposition upon the next input signals in order to compensate for both intrachannel and interchannel distortion.