Abstract: A method, and associated apparatus and computer program, to determine corrections for a parameter of interest, such as critical dimension, of a patterning process. The method includes determining an exposure control correction for an exposure control parameter and, optionally, determining a process control correction for a process control parameter, based upon a measurement of the parameter of interest of a structure, and an exposure control relationship and a process control relationship. The exposure control relationship describes the dependence of the parameter of interest on the exposure control parameter and the process control relationship describes the dependence of the parameter of interest on the process control parameter. The exposure control correction and process control correction may be co-optimized to minimize variation of the parameter of interest of subsequent exposed and processed structures relative to a target parameter of interest.

Abstract: A method, and associated apparatus and computer program, to determine corrections for a parameter of interest, such as critical dimension, of a patterning process. The method includes determining an exposure control correction for an exposure control parameter and, optionally, determining a process control correction for a process control parameter, based upon a measurement of the parameter of interest of a structure, and an exposure control relationship and a process control relationship. The exposure control relationship describes the dependence of the parameter of interest on the exposure control parameter and the process control relationship describes the dependence of the parameter of interest on the process control parameter. The exposure control correction and process control correction may be co-optimized to minimize variation of the parameter of interest of subsequent exposed and processed structures relative to a target parameter of interest.

Abstract: A method for fabricating interlevel contacts in semiconductor integrated circuits provides for formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

Abstract: A method is provided for forming a transistor spacer etch endpoint structure of an integrated circuit, and an integrated circuit formed according to the same. A gate is formed over a portion of a substrate. A dielectric layer is formed over the integrated circuit and an oxide layer is formed over the dielectric layer. The oxide layer is patterned and etched to form sidewall oxide spacers on each side of the gate and over a portion of the dielectric layer. The dielectric layer not covered by the sidewall oxide spacers is then removed.

Abstract: Interlevel contacts in semiconductor integrated circuits are fabricated by formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

Abstract: A method to reduce the effective recess in conductive plugs 220 by performing an oxide etch or oxide CMP, selective to the conductive material in question. This method can be used for any conductive plug 220 (e.g. aluminum, tungsten, copper, titanium nitride, etc.). In addition, this method is also applicable in contact, via, and trench (damascene) applications. Furthermore, this process can advantageously be used in logic, SRAM, and DRAM applications.

Abstract: A structure and method incorporating a CVD TiN barrier layer 230 over the aluminum plug 220 in order to prevent the high plug resistance caused by the blanket metal film stack 240, 250, and 260 deposition process. Unlike physical vapor deposited (PVD) TiN, CVD TiN 230 does not react with the aluminum 220 during annealing. CVD TiN has also been shown to be a better diffusion barrier for aluminum than PVD TiN. In addition, CVD TiN will disrupt any unfavorable grain boundary propagation through the aluminum plug which may act as a source of electromigration failure. Therefore, the CVD TiN 230 can increase the electromigration resistance, without increasing the contact/via resistance.

Abstract: A method is provided for forming a field programmable device of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed. A first, fusible, dielectric layer is formed over the first conductive layer. The dielectric layer is patterned and etched to form a plurality of dielectric regions exposing portions of the first conductive layer. A second dielectric layer is then formed over the dielectric regions and the exposed portions of the first conductive layer. A plurality of contact openings through the second dielectric layer are formed to expose portions of the first conductive layer and portions of the dielectric regions. A second conductive layer is then formed over the second dielectric layer and in the contact openings.

Abstract: A method for forming sloped contact corners of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A first oxide layer is formed over the integrated circuit. An insulating layer is formed over the oxide layer. The oxide and insulating layers are then patterned and etched to form a contact opening to expose a conductive region underlying a portion of the oxide layer. A second oxide layer is formed in the bottom of the contact opening. The insulating layer is then reflowed to form rounded contact corners after which the second oxide layer is removed.