Patents by Inventor Girish Bhat

Girish Bhat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11907138
    Abstract: Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: February 20, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Hiral Nandu, Subbarao Palacharla, George Patsilaras, Alain Artieri, Simon Peter William Booth, Vipul Gandhi, Girish Bhat, Yen-Kuan Wu, Younghoon Kim
  • Patent number: 11803472
    Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: October 31, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Girish Bhat, Subbarao Palacharla, Jeffrey Shabel, Isaac Berk, Kedar Bhole, Vipul Gandhi, George Patsilaras, Sparsh Singhai
  • Patent number: 11783042
    Abstract: Resource access control in a system-on-chip (“SoC”) may employ an agent executing on a processor of the SoC and a trust management engine of the SoC. The agent, such as, for example, a high-level operating system or a hypervisor, may be configured to allocate a resource comprising a memory region to an access domain and to load a software image associated with the access domain into the memory region. The trust management engine may be configured to lock the resource against access by any entity other than the access domain, to authenticate the software image associated with the access domain, and to initiate booting of the access domain in response to a successful authentication of the software image associated with the access domain.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: October 10, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Steven Halter, Samar Asbe, Miguel Ballesteros, Girish Bhat, Mahadevamurty Nemani
  • Publication number: 20230214330
    Abstract: Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.
    Type: Application
    Filed: December 31, 2021
    Publication date: July 6, 2023
    Inventors: Hiral NANDU, Subbarao PALACHARLA, George PATSILARAS, Alain ARTIERI, Simon Peter William BOOTH, Vipul GANDHI, Girish BHAT, Yen-Kuan WU, Younghoon KIM
  • Publication number: 20230029696
    Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Inventors: Girish Bhat, Subbarao Palacharla, Jeffrey Shabel, Isaac Berk, Kedar Bhole, Vipul Gandhi, George Patsilaras, Sparsh Singhai
  • Patent number: 11295765
    Abstract: A data storage device is disclosed comprising a first plurality of heads actuated over a first subset of disk surfaces by a first servo control loop comprising a first coarse actuator and a first fine actuator, and a second plurality of heads actuated over a second subset of the disk surfaces by a second servo control loop comprising a second coarse actuator and a second fine actuator. A plurality of access commands are received, wherein each access command is associated with one of the heads. While executing a first access command using the first servo control loop, a disturbance is ramped while injecting the disturbance into the second servo control loop, and the second fine actuator is calibrated based on the disturbance.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: April 5, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Kun Zhang, Shravankumar Girish Bhat, Shrey Khanna
  • Publication number: 20210397714
    Abstract: Resource access control in a system-on-chip (“SoC”) may employ an agent executing on a processor of the SoC and a trust management engine of the SoC. The agent, such as, for example, a high-level operating system or a hypervisor, may be configured to allocate a resource comprising a memory region to an access domain and to load a software image associated with the access domain into the memory region. The trust management engine may be configured to lock the resource against access by any entity other than the access domain, to authenticate the software image associated with the access domain, and to initiate booting of the access domain in response to a successful authentication of the software image associated with the access domain.
    Type: Application
    Filed: June 17, 2020
    Publication date: December 23, 2021
    Inventors: Steven HALTER, Samar ASBE, Miguel BALLESTEROS, Girish BHAT, Mahadevamurty NEMANI
  • Publication number: 20210365557
    Abstract: A method for external access control to protect system-on-chip (SoC) subsystems and stored subsystem assets is described. The method includes sensing, during a cold boot of an SoC hardware system, a debug fuse vector for access to SoC subsystems of an SoC owner and/or third-party subsystems of an SoC hardware architecture. The method also includes disabling access to each SoC subsystem with a blown fuse in the debug fuse vector. The method further includes re-enabling, by a secure root of trust, access to an SoC subsystem and/or a third-party subsystem for an external debugger when authentication of one or more debug certificates of a third-party owner of the external debugger is successful.
    Type: Application
    Filed: May 21, 2020
    Publication date: November 25, 2021
    Inventors: Jaydeep CHOKSHI, Miguel BALLESTEROS, Mahadevamurty NEMANI, Samar ASBE, Girish BHAT, Alan YOUNG, Victor WONG, Steven HALTER
  • Patent number: 10038567
    Abstract: Methods, apparatus and data structures are provided for managing multicast IP flows. According to one embodiment, a router identifies active multicast IP sessions. A data structure is maintained by the router that contains information regarding the active multicast IP sessions and includes multiple pairs of a source field and a group field ({S, G} pairs), a first pointer associated with each of the {S,G} pairs and a set of slots. Each of the {S, G} pairs defines an active multicast IP session. The source field defines a source of a multicast transmission of the multicast IP session and the group field defines a group corresponding to the multicast IP session. The first pointer points to a dynamically allocated set of outbound interface (OIF) blocks. Each slot has stored therein a second pointer to a transmit control block (TCB) data structure that services users participating in the multicast IP session.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: July 31, 2018
    Assignee: Fortinet, Inc.
    Inventors: Rajesh I. Balay, Girish Bhat, Gregory Lockwood, Rama Krishnam Nagarajan
  • Publication number: 20160226670
    Abstract: Methods, apparatus and data structures are provided for managing multicast IP flows. According to one embodiment, a router identifies active multicast IP sessions. A data structure is maintained by the router that contains information regarding the active multicast IP sessions and includes multiple pairs of a source field and a group field ({S, G} pairs), a first pointer associated with each of the {S,G} pairs and a set of slots. Each of the {S, G} pairs defines an active multicast IP session. The source field defines a source of a multicast transmission of the multicast IP session and the group field defines a group corresponding to the multicast IP session. The first pointer points to a dynamically allocated set of outbound interface (OIF) blocks. Each slot has stored therein a second pointer to a transmit control block (TCB) data structure that services users participating in the multicast IP session.
    Type: Application
    Filed: April 12, 2016
    Publication date: August 4, 2016
    Applicant: Fortinet, Inc.
    Inventors: Rajesh I. Balay, Girish Bhat, Gregory Lockwood, Rama Krishnam Nagarajan
  • Patent number: 9319303
    Abstract: Methods, apparatus and data structures are provided for managing multicast IP flows. According to one embodiment, a router identifies active multicast IP sessions. A data structure is maintained by the router that contains information regarding the active multicast IP sessions and includes multiple pairs of a source field and a group field ({S, G} pairs), a first pointer associated with each of the {S,G} pairs and a set of slots. Each of the {S, G} pairs defines an active multicast IP session. The source field defines a source of a multicast transmission of the multicast IP session and the group field defines a group corresponding to the multicast IP session. The first pointer points to a dynamically allocated set of outbound interface (OIF) blocks. Each slot has stored therein a second pointer to a transmit control block (TCB) data structure that services users participating in the multicast IP session.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: April 19, 2016
    Assignee: Fortinet, Inc.
    Inventors: Rajesh I. Balay, Girish Bhat, Gregory Lockwood, Rama Krishnam Nagarajan
  • Patent number: 9304844
    Abstract: One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 5, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kapil Bansal, Girish Bhat, Subodh Singh, Victor Wong, Pradeep Atur
  • Publication number: 20160020994
    Abstract: Methods, apparatus and data structures are provided for managing multicast IP flows. According to one embodiment, a router identifies active multicast IP sessions. A data structure is maintained by the router that contains information regarding the active multicast IP sessions and includes multiple pairs of a source field and a group field ({S, G} pairs), a first pointer associated with each of the {S,G} pairs and a set of slots. Each of the {S, G} pairs defines an active multicast IP session. The source field defines a source of a multicast transmission of the multicast IP session and the group field defines a group corresponding to the multicast IP session. The first pointer points to a dynamically allocated set of outbound interface (OIF) blocks. Each slot has stored therein a second pointer to a transmit control block (TCB) data structure that services users participating in the multicast IP session.
    Type: Application
    Filed: September 26, 2015
    Publication date: January 21, 2016
    Applicant: FORTINET, INC.
    Inventors: Rajesh I. Balay, Girish Bhat, Gregory Lockwood, Rama Krishnam Nagarajan
  • Patent number: 9166805
    Abstract: Methods, apparatus and data structures are provided for managing multicast IP flows. According to one embodiment, a network switch module includes a memory and multiple processors partitioned among multiple virtual routers (VRs). Each VR maintains a data structure containing therein information regarding the multicast sessions, including a first value for each of the multicast sessions, at least one chain of one or more blocks of second values and one or more transmit control blocks (TCBs). Each first value is indicative of a chain of one or more blocks of second values. Each second value corresponds to an outbound interface (OIF) participating in the multicast session and identifies a number of times packets associated with the multicast session are to be replicated. The TCBs have stored therein control information to process or route packets. Each second value is indicative of a TCB that identifies an OIF of the network device through which packets are to be transmitted.
    Type: Grant
    Filed: May 16, 2015
    Date of Patent: October 20, 2015
    Assignee: Fortinet, Inc.
    Inventors: Rajesh I. Balay, Girish Bhat, Gregory Lockwood, Rama Krishnam Nagarajan
  • Patent number: 9167016
    Abstract: Methods, apparatus and data structures are provided for managing multicast IP flows. According to one embodiment, active multicast IP sessions are identified by a network device. A data structure is maintained by the network device and contains therein information regarding the multicast sessions, including a first value for each of the multicast sessions, at least one chain of one or more blocks of second values and one or more transmit control blocks (TCBs). Each first value is indicative of a chain of one or more blocks of second values. Each second value corresponds to an outbound interface (OIF) participating in the multicast session and identifies a number of times packets associated with the multicast session are to be replicated. The TCBs have stored therein control information to process or route packets. Each second value is indicative of a TCB that identifies an OIF of the network device through which packets are to be transmitted.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: October 20, 2015
    Assignee: Fortinet, Inc.
    Inventors: Rajesh I. Balay, Girish Bhat, Gregory Lockwood, Rama Krishnam Nagarajan
  • Publication number: 20150280929
    Abstract: Methods, apparatus and data structures are provided for managing multicast IP flows. According to one embodiment, a network switch module includes a memory and multiple processors partitioned among multiple virtual routers (VRs). Each VR maintains a data structure containing therein information regarding the multicast sessions, including a first value for each of the multicast sessions, at least one chain of one or more blocks of second values and one or more transmit control blocks (TCBs). Each first value is indicative of a chain of one or more blocks of second values. Each second value corresponds to an outbound interface (OIF) participating in the multicast session and identifies a number of times packets associated with the multicast session are to be replicated. The TCBs have stored therein control information to process or route packets. Each second value is indicative of a TCB that identifies an OIF of the network device through which packets are to be transmitted.
    Type: Application
    Filed: May 16, 2015
    Publication date: October 1, 2015
    Applicant: Fortinet, Inc.
    Inventors: Rajesh I. Balay, Girish Bhat, Gregory Lockwood, Rama Krishnam Nagarajan
  • Publication number: 20150156234
    Abstract: Methods, apparatus and data structures are provided for managing multicast IP flows. According to one embodiment, active multicast IP sessions are identified by a network device. A data structure is maintained by the network device and contains therein information regarding the multicast sessions, including a first value for each of the multicast sessions, at least one chain of one or more blocks of second values and one or more transmit control blocks (TCBs). Each first value is indicative of a chain of one or more blocks of second values. Each second value corresponds to an outbound interface (OIF) participating in the multicast session and identifies a number of times packets associated with the multicast session are to be replicated. The TCBs have stored therein control information to process or route packets. Each second value is indicative of a TCB that identifies an OIF of the network device through which packets are to be transmitted.
    Type: Application
    Filed: February 6, 2015
    Publication date: June 4, 2015
    Applicant: FORTINET, INC.
    Inventors: Rajesh I. Balay, Girish Bhat, Gregory Lockwood, Rama Krishnam Nagarajan
  • Publication number: 20150079909
    Abstract: In one configuration, an apparatus and a method to operate the apparatus are provided. The apparatus includes at least one processor configured to receive operating information indicating a set of operating frequencies from a first circuit and to select an operating frequency from the set of operating frequencies. The at least one processor is further arranged to configure an operation of a second circuit based on the selected operating frequency. In another configuration, the apparatus includes at least one processor configured to select a set of operating frequencies based a radio frequency operation and to transmit operating information indicating the set of operating frequencies to a control circuit.
    Type: Application
    Filed: June 11, 2014
    Publication date: March 19, 2015
    Inventors: Carlos SOLEDADE, Ajay BAWALE, Graham ROFF, Girish BHAT
  • Patent number: 8953513
    Abstract: Methods, apparatus and data structures are provided for managing multicast IP flows. According to one embodiment, active multicast IP sessions are identified by a router. A data structure is maintained by the router and contains therein information regarding the multicast sessions, including a first pointer for each of the multicast sessions, at least one chain of one or more blocks of second pointers and one or more transmit control blocks (TCBs). Each first pointer points to a chain of one or more blocks of second pointers. Each second pointer corresponds to an outbound interface (OIF) participating in the multicast session and identifies a number of times packets associated with the multicast session are to be replicated. The TCBs have stored therein control information to process or route packets. Each second pointer points to a TCB that identifies an OIF of the router through which packets are to be transmitted.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: February 10, 2015
    Assignee: Fortinet, Inc.
    Inventors: Rajesh I. Balay, Girish Bhat, Gregory Lockwood, Rama Krishnam Nagarajan
  • Publication number: 20140245076
    Abstract: One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Kapil Bansal, Girish Bhat, Subodh Singh, Victor Wong, Pradeep Atur