Patents by Inventor Girish Desai

Girish Desai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240069772
    Abstract: A storage operation die collision avoidance system includes a storage subsystem providing a first superblock and a second superblock. A storage operation subsystem is coupled to the storage subsystem and performs first storage operations for the first superblock using a first die in the storage subsystem. The storage operation subsystem then determines second storage operations for performance for the second superblock and, without a fixed die storage operation order, identifies a second die in the storage subsystem that is available to perform the second storage operations for the second superblock while at least some of the first storage operations are performed for the first superblock using the first die in the storage subsystem. The storage operation subsystem then performs the second storage operations for the second superblock using the second die in the storage subsystem.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Girish Desai, Frederick K.H. Lee, Dody Suratman
  • Patent number: 11847326
    Abstract: A storage operation suspend system includes a chassis having a storage operation suspend subsystem coupled to a communication system and a storage subsystem in the chassis. The storage operation suspend subsystem performs a first storage operation on a storage die in the storage subsystem, receives a second storage operation instruction via the communication system to perform a second storage operation on the storage die, determines that the second storage operation is a higher priority operation than the first storage operation, determines that a first power amount available in a power budget and a second power amount allocated from the power budget to the first storage operation is sufficient to perform the second storage operation when the first storage operation is suspended and, in response, suspends the first storage operation and performs the second storage operation and, following completion of the second storage operation, resumes performance of the first storage operation.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: December 19, 2023
    Assignee: Dell Products L.P.
    Inventors: Girish Desai, Frederick K. H. Lee
  • Patent number: 11836073
    Abstract: A counter system includes a counter management subsystem, a storage subsystem having storage elements, and a non-volatile memory system storing a first counter including a first value field/first bitmap field combination for each storage element, and a second counter including a second value field/second bitmap field combination for each storage element. The counter management subsystem resets the first counter and, following each storage operation on a storage element, updates a bit in the first bitmap field for that storage element. When one of the first bitmap fields is filled, the counter management subsystem converts each first value field/first bitmap field combination to a respective first value, resets the second counter, updates the second value field for each storage element with the respective first value for each storage element and, following each storage operation on a storage element, updates a bit in the second bitmap field for that storage element.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: December 5, 2023
    Assignee: Dell Products L.P.
    Inventors: Alex Liu, Girish Desai, Leland W. Thompson
  • Patent number: 11822429
    Abstract: A storage device RAID data write intermediate parity system includes a storage device coupled to a host system and including a storage subsystem and a volatile memory system. The storage device RAID data write intermediate parity system receives first primary data from the host system, and stores the first primary data in the volatile memory system. The storage device RAID data write intermediate parity system then stores a first subset of the first primary data in the storage system, generates first intermediate parity data using the first subset of the first primary data, stores the first intermediate parity data in the volatile memory system and, in response, erases the first subset of the first primary data from the volatile memory system.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: November 21, 2023
    Assignee: Dell Products L.P.
    Inventors: Girish Desai, Frederick K. H. Lee
  • Publication number: 20230350584
    Abstract: A storage operation suspend system includes a chassis having a storage operation suspend subsystem coupled to a communication system and a storage subsystem in the chassis. The storage operation suspend subsystem performs a first storage operation on a storage die in the storage subsystem, receives a second storage operation instruction via the communication system to perform a second storage operation on the storage die, determines that the second storage operation is a higher priority operation than the first storage operation, determines that a first power amount available in a power budget and a second power amount allocated from the power budget to the first storage operation is sufficient to perform the second storage operation when the first storge operation is suspended and, in response, suspends the first storage operation and performs the second storage operation and, following completion of the second storage operation, resumes performance of the first storage operation.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Inventors: Girish Desai, Frederick K.H. Lee
  • Publication number: 20230350796
    Abstract: A counter system includes a counter management subsystem, a storage subsystem having storage elements, and a non-volatile memory system storing a first counter including a first value field/first bitmap field combination for each storage element, and a second counter including a second value field/second bitmap field combination for each storage element. The counter management subsystem resets the first counter and, following each storage operation on a storage element, updates a bit in the first bitmap field for that storage element. When one of the first bitmap fields is filled, the counter management subsystem converts each first value field/first bitmap field combination to a respective first value, resets the second counter, updates the second value field for each storage element with the respective first value for each storage element and, following each storage operation on a storage element, updates a bit in the second bitmap field for that storage element.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Inventors: Alex Liu, Girish Desai, Leland W. Thompson
  • Publication number: 20230325278
    Abstract: A storage device RAID data write intermediate parity system includes a storage device coupled to a host system and including a storage subsystem and a volatile memory system. The storage device RAID data write intermediate parity system receives first primary data from the host system, and stores the first primary data in the volatile memory system. The storage device RAID data write intermediate parity system then stores a first subset of the first primary data in the storage system, generates first intermediate parity data using the first subset of the first primary data, stores the first intermediate parity data in the volatile memory system and, in response, erases the first subset of the first primary data from the volatile memory system.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Inventors: Girish Desai, Frederick K.H. Lee
  • Patent number: 11733926
    Abstract: Systems and methods provide improved bus efficiency in read operations by a solid-state device (SSD) installed in an Information Handling System. A read operation is received that requests data stored in a die of the SSD. A command is issued to the die for use of a first read voltage in retrieving the requested data. Upon receiving confirmation that the die has retrieved the requested data, a command is issued to the die to configure a second read voltage for use in retrieving data requested by a second read operation received by the SSD. Concurrent with the die setting the second read voltage for use in retrieving the data requested in the second read operation, a command is issued to initiating transfer, by the die, of the data retrieved for the first read operation. In this manner, idle intervals in the bus used to service the die are eliminated.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: August 22, 2023
    Assignee: Dell Products, L.P.
    Inventors: Girish Desai, Frederick Lee
  • Publication number: 20230195972
    Abstract: Systems and methods for autonomous vehicle (AV) simulation and code build scheduling are provided. A method includes receiving a first task specification for a first task associated with a first AV simulation and/or a first AV code build, receiving, a second task specification for a second task associated with a second AV simulation and/or a second AV code build, and executing a portion of the first task concurrently with a portion of the second task based on the portion of the first task and the portion of the second task have different resource requirements. The portion of the first task is associated with one of an AV asset download, an AV code execution, or an AV artifact upload. The portion of the second task is associated with a different one of the AV asset download, the AV code execution, or the AV artifact upload.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Applicant: GM Cruise Holdings LLC
    Inventors: Amit Girish Desai, Michael Storm, Ian Harrison Markowtiz
  • Publication number: 20230195959
    Abstract: Systems and methods for autonomous vehicle (AV) simulation and code build scheduling are provided. A method includes receiving a first task specification for a first task associated with a first AV simulation and/or a first AV code build, receiving, a second task specification for a second task associated with a second AV simulation and/or a second AV code build, and executing a portion of the first task concurrently with a portion of the second task based on the portion of the first task and the portion of the second task have different resource requirements. The portion of the first task is associated with one of an AV asset download, an AV code execution, or an AV artifact upload. The portion of the second task is associated with a different one of the AV asset download, the AV code execution, or the AV artifact upload.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Applicant: GM Cruise Holdings LLC
    Inventors: Amit Girish Desai, Michael Storm, Ian Harrison Markowtiz
  • Publication number: 20230142986
    Abstract: A wireless network system is described. In some scenarios MME/MSC/SGSN may act as a client which has huge amount of real-time data to be delivered towards server. For this speedy and reliable delivery requirement, a approach has been proposed which will use multiple parallel HTTP connections for delivery and also make sure that the events related to a particular node is delivered in right order. The multiple HTTP connections are used for parallel delivery so that in case one connections fails then it may not impact other existing connections. The number of connections may grow dynamically up to the configured limit depending on the data delivery requirements and then it may dynamically shrink once the load is reduced. A key based approach is proposed where each connected node will be assigned a unique key which will be used for sequencing the messages related to events of this particular node.
    Type: Application
    Filed: November 7, 2022
    Publication date: May 11, 2023
    Inventors: Mukesh Singhal, Girish Desai, Raghu Kota
  • Publication number: 20230114146
    Abstract: Systems and methods provide improved bus efficiency in read operations by a solid-state device (SSD) installed in an Information Handling System. A read operation is received that requests data stored in a die of the SSD. A command is issued to the die for use of a first read voltage in retrieving the requested data. Upon receiving confirmation that the die has retrieved the requested data, a command is issued to the die to configure a second read voltage for use in retrieving data requested by a second read operation received by the SSD. Concurrent with the die setting the second read voltage for use in retrieving the data requested in the second read operation, a command is issued to initiating transfer, by the die, of the data retrieved for the first read operation. In this manner, idle intervals in the bus used to service the die are eliminated.
    Type: Application
    Filed: October 8, 2021
    Publication date: April 13, 2023
    Applicant: Dell Products, L.P.
    Inventors: Girish Desai, Frederick Lee
  • Publication number: 20230075944
    Abstract: A method is disclosed for client-server reconciliation for wireless telecommunication networks, comprising: determining, by a client system in a Radio Access Network (RAN) connected to a server in the RAN, a need for reconciliation with the server; terminating an HTTP connection; flushing a buffer; creating a current snapshot of the client system; sending the current snapshot to the server with an identifier for a particular server process; buffering a message at the client during reconciliation; sending a reconciliation complete message to the server to indicate that process has been completed and all the data from the client has been delivered to the server; and sending, by the client after the reconciliation is complete, the message that was buffered during the reconciliation to the server.
    Type: Application
    Filed: August 15, 2022
    Publication date: March 9, 2023
    Inventors: Girish Desai, Mukesh Singhal, Raghu Kota
  • Publication number: 20220214834
    Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the fir
    Type: Application
    Filed: March 21, 2022
    Publication date: July 7, 2022
    Inventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
  • Patent number: 11294594
    Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the fir
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 5, 2022
    Assignee: Kioxia Corporation
    Inventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
  • Patent number: 10909030
    Abstract: In an SSD including a host interface, controller, non-volatile memory coupled to the controller, and volatile memory, data is stored in non-volatile memory in clusters having a cluster start address and a cluster end address. A mapping table is maintained in volatile memory, which indicates by a trim signature deallocated clusters in non-volatile memory. The trim table is populated with deallocated ranges and an associated offset within the non-volatile memory. The controller receives from the host interface a sequence of commands including a deallocate command including at least one address range including a start address and an end address, or a start address and a length of the address range. The controller processes the deallocate command by selecting one or both of a write-to-non-volatile-memory action and a record-to-volatile-memory action. In cases of power failure, the mapping table is restored for deallocated ranges at specific offsets recorded in the trim table.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Girish Desai, Saswati Das, Senthil Thangaraj, Barada Mishra, Julien Magretts, Philip Rose
  • Patent number: 10713163
    Abstract: A method of managing a solid state drive (SSD), comprising: storing a first set of data in a first plurality of non-volatile memory dies, the first plurality of non-volatile memory dies communicatively arranged in one or more first communication channels; storing a second set of data in a second plurality of non-volatile memory dies, the second plurality of non-volatile memory dies communicatively arranged in one or more second communication channels; generating a first set of system data corresponding only to the first set of data; generating a second set of system data corresponding only to the second set of data; and managing the first set of system data corresponding to the first set of data independently of the second set of system data corresponding to the second set of data, wherein the one or more first communication channel and the one or more second communication channel are communicatively coupled to one or more channel controllers, the one or more channel controls are communicatively coupled to a
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: July 14, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Girish Desai, Narasimhulu DharaniKumar Kotte
  • Publication number: 20200081830
    Abstract: In an SSD including a host interface, controller, non-volatile memory coupled to the controller, and volatile memory, data is stored in non-volatile memory in clusters having a cluster start address and a cluster end address. A mapping table is maintained in volatile memory, which indicates by a trim signature deallocated clusters in non-volatile memory. The trim table is populated with deallocated ranges and an associated offset within the non-volatile memory. The controller receives from the host interface a sequence of commands including a deallocate command including at least one address range including a start address and an end address, or a start address and a length of the address range. The controller processes the deallocate command by selecting one or both of a write-to-non-volatile-memory action and a record-to-volatile-memory action. In cases of power failure, the mapping table is restored for deallocated ranges at specific offsets recorded in the trim table.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 12, 2020
    Inventors: Girish Desai, Saswati Das, Senthil Thangaraj, Barada Mishra, Julien Magretts, Philip Rose
  • Publication number: 20200081834
    Abstract: A method of managing a solid state drive (SSD), comprising: storing a first set of data in a first plurality of non-volatile memory dies, the first plurality of non-volatile memory dies communicatively arranged in one or more first communication channels; storing a second set of data in a second plurality of non-volatile memory dies, the second plurality of non-volatile memory dies communicatively arranged in one or more second communication channels; generating a first set of system data corresponding only to the first set of data; generating a second set of system data corresponding only to the second set of data; and managing the first set of system data corresponding to the first set of data independently of the second set of system data corresponding to the second set of data, wherein the one or more first communication channel and the one or more second communication channel are communicatively coupled to one or more channel controllers, the one or more channel controls are communicatively coupled to a
    Type: Application
    Filed: September 11, 2018
    Publication date: March 12, 2020
    Inventors: Girish Desai, Narasimhulu DharaniKumar Kotte
  • Patent number: 10248587
    Abstract: Methods and systems are provided that execute reduced host data commands. A reduced host data command may be a write command that includes or is received with an indication of host data instead of the host data. The reduced host data command may be executed with a Direct Memory Access (DMA) circuit independently of a processor that executes administrative commands. In the execution of the reduced host data command, host data may be generated, metadata may be generated, and the generated host data and/or metadata may be copied into backend memory with the DMA circuit independently of the processor.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: April 2, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Shay Benisty, Tal Sharifie, Girish Desai, Oded Karni