Patents by Inventor Girish G. Kurup
Girish G. Kurup has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11372776Abstract: The present disclosure relates to a method of operating a translation lookaside buffer (TLB) arrangement for a processor supporting virtual addressing, wherein multiple translation engines are used to perform translations on request of one of a plurality of dedicated processor units. The method comprises: maintaining by a cache unit a dependency matrix for the engines to track for each processing unit if an engine is assigned to the each processing unit for a table walk. The cache unit may block a processing unit from allocating an engine to a translation request when the engine is already assigned to the processing unit in the dependency matrix.Type: GrantFiled: December 9, 2019Date of Patent: June 28, 2022Assignee: International Business Machines CorporationInventors: Michael Johannes Jaspers, Markus Kaltenbach, Girish G. Kurup, Ulrich Mayer
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Patent number: 11223369Abstract: Compressing data includes hashing a first token length of an incoming data steam into a hash table, where the first token length includes a plurality of bytes. A second token length of the incoming data stream may be hashed into the hash table. The second token may be larger than the first token length and includes the plurality of bytes. The method may further include automatically comparing which token length enabled more efficient data compression, and automatically adjusting at least one of the first and second token lengths based on the comparison.Type: GrantFiled: April 2, 2019Date of Patent: January 11, 2022Assignee: International Business Machines CorporationInventors: Bulent Abali, Ashutosh Misra, Girish G. Kurup, Deepankar Bhattacharjee, Matthias Klein
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Publication number: 20200321976Abstract: Compressing data includes hashing a first token length of an incoming data steam into a hash table, where the first token length includes a plurality of bytes. A second token length of the incoming data stream may be hashed into the hash table. The second token may be larger than the first token length and includes the plurality of bytes. The method may further include automatically comparing which token length enabled more efficient data compression, and automatically adjusting at least one of the first and second token lengths based on the comparison.Type: ApplicationFiled: April 2, 2019Publication date: October 8, 2020Inventors: Bulent ABALI, Ashutosh MISRA, Girish G. KURUP, Deepankar BHATTACHARJEE, Matthias KLEIN
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Patent number: 10649912Abstract: The present disclosure relates to a method of operating a translation lookaside buffer (TLB) arrangement for a processor supporting virtual addressing, wherein multiple translation engines are used to perform translations on request of one of a plurality of dedicated processor units. The method comprises: maintaining by a cache unit a dependency matrix for the engines to track for each processing unit if an engine is assigned to the each processing unit for a table walk. The cache unit may block a processing unit from allocating an engine to a translation request when the engine is already assigned to the processing unit in the dependency matrix.Type: GrantFiled: July 14, 2017Date of Patent: May 12, 2020Assignee: International Business Machines CorporationInventors: Michael Johannes Jaspers, Markus Kaltenbach, Girish G. Kurup, Ulrich Mayer
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Publication number: 20200110711Abstract: The present disclosure relates to a method of operating a translation lookaside buffer (TLB) arrangement for a processor supporting virtual addressing, wherein multiple translation engines are used to perform translations on request of one of a plurality of dedicated processor units. The method comprises: maintaining by a cache unit a dependency matrix for the engines to track for each processing unit if an engine is assigned to the each processing unit for a table walk. The cache unit may block a processing unit from allocating an engine to a translation request when the engine is already assigned to the processing unit in the dependency matrix.Type: ApplicationFiled: December 9, 2019Publication date: April 9, 2020Inventors: Michael Johannes Jaspers, Markus Kaltenbach, Girish G. Kurup, Ulrich Mayer
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Patent number: 10592414Abstract: Improving access to a cache by a processing unit. One or more previous requests to access data from a cache are stored. A current request to access data from the cache is retrieved. A determination is made whether the current request is seeking the same data from the cache as at least one of the one or more previous requests. A further determination is made whether the at least one of the one or more previous requests seeking the same data was successful in arbitrating access to a processing unit when seeking access. A next cache write access is suppressed if the at least one of previous requests seeking the same data was successful in arbitrating access to the processing unit.Type: GrantFiled: July 14, 2017Date of Patent: March 17, 2020Assignee: International Business Machines CorporationInventors: Simon H. Friedmann, Girish G. Kurup, Markus Kaltenbach, Ulrich Mayer, Martin Recktenwald
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Patent number: 10540293Abstract: The present disclosure relates to a method of operating a translation lookaside buffer (TLB) arrangement for a processor supporting virtual addressing, wherein multiple translation engines are used to perform translations on request of one of a plurality of dedicated processor units. The method comprises: maintaining by a cache unit a dependency matrix for the engines to track for each processing unit if an engine is assigned to the each processing unit for a table walk. The cache unit may block a processing unit from allocating an engine to a translation request when the engine is already assigned to the processing unit in the dependency matrix.Type: GrantFiled: December 15, 2017Date of Patent: January 21, 2020Assignee: International Business Machines CorporationInventors: Michael Johannes Jaspers, Markus Kaltenbach, Girish G. Kurup, Ulrich Mayer
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Patent number: 10423546Abstract: A method for coupling transactions with a configurable ordering controller in a computer system. The method comprises sending, by a coupling device, first data packets with an unordered attribute being set to an ordering controller. The method further comprises sending, by the coupling device, second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The method further comprises sending, by the ordering controller, the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.Type: GrantFiled: November 8, 2017Date of Patent: September 24, 2019Assignee: International Business Machines CorporationInventors: Norbert Hagspiel, Sascha Junghans, Matthias Klein, Girish G. Kurup
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Patent number: 10353833Abstract: A computer system with a configurable ordering controller for coupling transactions. The computer system comprises a coupling device configured to send first data packets with an unordered attribute being set to an ordering controller. The computer system further comprises the coupling device configured to send second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The computer system further comprises the ordering controller configured to send the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.Type: GrantFiled: July 11, 2017Date of Patent: July 16, 2019Assignee: International Business Machines CorporationInventors: Norbert Hagspiel, Sascha Junghans, Matthias Klein, Girish G. Kurup
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Publication number: 20190018796Abstract: The present disclosure relates to a method of operating a translation lookaside buffer (TLB) arrangement for a processor supporting virtual addressing, wherein multiple translation engines are used to perform translations on request of one of a plurality of dedicated processor units. The method comprises: maintaining by a cache unit a dependency matrix for the engines to track for each processing unit if an engine is assigned to the each processing unit for a table walk. The cache unit may block a processing unit from allocating an engine to a translation request when the engine is already assigned to the processing unit in the dependency matrix.Type: ApplicationFiled: December 15, 2017Publication date: January 17, 2019Inventors: Michael Johannes Jaspers, Markus Kaltenbach, Girish G. Kurup, Ulrich Mayer
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Publication number: 20190018779Abstract: Improving access to a cache by a processing unit. One or more previous requests to access data from a cache are stored. A current request to access data from the cache is retrieved. A determination is made whether the current request is seeking the same data from the cache as at least one of the one or more previous requests. A further determination is made whether the at least one of the one or more previous requests seeking the same data was successful in arbitrating access to a processing unit when seeking access. A next cache write access is suppressed if the at least one of previous requests seeking the same data was successful in arbitrating access to the processing unit.Type: ApplicationFiled: July 14, 2017Publication date: January 17, 2019Inventors: Simon H. Friedmann, Girish G. Kurup, Markus Kaltenbach, Ulrich Mayer, Martin Recktenwald
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Publication number: 20190018795Abstract: The present disclosure relates to a method of operating a translation lookaside buffer (TLB) arrangement for a processor supporting virtual addressing, wherein multiple translation engines are used to perform translations on request of one of a plurality of dedicated processor units. The method comprises: maintaining by a cache unit a dependency matrix for the engines to track for each processing unit if an engine is assigned to the each processing unit for a table walk. The cache unit may block a processing unit from allocating an engine to a translation request when the engine is already assigned to the processing unit in the dependency matrix.Type: ApplicationFiled: July 14, 2017Publication date: January 17, 2019Inventors: Michael Johannes Jaspers, Markus Kaltenbach, Girish G. Kurup, Ulrich Mayer
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Patent number: 10097600Abstract: A method for analyzing streaming data includes providing a streaming accumulator comprising an addition module and two multiplexers, receiving one or more data streams, continuously calculating a set of basic statistical elements, receiving a request to calculate a set of statistical descriptors, calculating the set of statistical descriptors, and providing the set of statistical descriptors. An apparatus for analyzing streaming data includes a first multiplexer configured to receive a first summation, a second summation, and a current data item, and forward the first summation on cycles 1 and 3, forward the second summation on cycle 4, and forward the current data item on cycle 2, a second multiplexer configured to receiver the second summation, a third summation, and a previous data item, and forward the previous data item on cycles 1 and 3, forward the second summation on cycle 4, and forward the third summation on cycle 2.Type: GrantFiled: July 21, 2016Date of Patent: October 9, 2018Assignee: International Business Machines CorporationInventors: Suchismita Banerjee, Girish G. Kurup, Ashutosh Misra, Niranjan Vaish
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Patent number: 10089231Abstract: Improving access to a cache by a processing unit. One or more previous requests to access data from a cache are stored. A current request to access data from the cache is retrieved. A determination is made whether the current request is seeking the same data from the cache as at least one of the one or more previous requests. A further determination is made whether the at least one of the one or more previous requests seeking the same data was successful in arbitrating access to a processing unit when seeking access. A next cache write access is suppressed if the at least one of previous requests seeking the same data was successful in arbitrating access to the processing unit.Type: GrantFiled: November 7, 2017Date of Patent: October 2, 2018Assignee: International Business Machines CorporationInventors: Simon H. Friedmann, Girish G. Kurup, Markus Kaltenbach, Ulrich Mayer, Martin Recktenwald
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Patent number: 10033778Abstract: A method for analyzing streaming data includes providing a streaming accumulator comprising an addition module and two multiplexers, receiving one or more data streams, continuously calculating a set of basic statistical elements, receiving a request to calculate a set of statistical descriptors, calculating the set of statistical descriptors, and providing the set of statistical descriptors. An apparatus for analyzing streaming data includes a first multiplexer configured to receive a first summation, a second summation, and a current data item, and forward the first summation on cycles 1 and 3, forward the second summation on cycle 4, and forward the current data item on cycle 2, a second multiplexer configured to receiver the second summation, a third summation, and a previous data item, and forward the previous data item on cycles 1 and 3, forward the second summation on cycle 4, and forward the third summation on cycle 2.Type: GrantFiled: September 29, 2015Date of Patent: July 24, 2018Assignee: International Business Machines CorporationInventors: Suchismita Banerjee, Girish G. Kurup, Ashutosh Misra, Niranjan Vaish
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Patent number: 9667564Abstract: A method and system are provided for implementing a hierarchical high radix switch with a time-sliced crossbar. The hierarchical high radix switch includes a plurality of inputs and a plurality of outputs. Each input belongs to one input group; each input group sends consolidated requests to each output, by ORing the requests from the local input ports in that input group. Each output port belongs to one output group; each output port grants one of the requesting input groups using a rotating priority defined by a next-to-serve pointer. Each output group consolidates the output port grants and allows one grant to pass back to an input group. Each input port in an input group evaluates all incoming grants in an oldest packet first manner to form an accept. Each input group consolidates the input port accepts and selects one accept to send to the output port.Type: GrantFiled: August 28, 2013Date of Patent: May 30, 2017Assignee: International Business Machines CorporationInventors: Nikolaos Chrysos, Girish G. Kurup, Cyriel J. Minkenberg, Anil Pothireddy, Mark L. Rudquist, Vibhor K. Srivastava, Brian T. Vanderpool
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Publication number: 20170093655Abstract: A method for analyzing streaming data includes providing a streaming accumulator comprising an addition module and two multiplexers, receiving one or more data streams, continuously calculating a set of basic statistical elements, receiving a request to calculate a set of statistical descriptors, calculating the set of statistical descriptors, and providing the set of statistical descriptors. An apparatus for analyzing streaming data includes a first multiplexer configured to receive a first summation, a second summation, and a current data item, and forward the first summation on cycles 1 and 3, forward the second summation on cycle 4, and forward the current data item on cycle 2, a second multiplexer configured to receiver the second summation, a third summation, and a previous data item, and forward the previous data item on cycles 1 and 3, forward the second summation on cycle 4, and forward the third summation on cycle 2.Type: ApplicationFiled: September 29, 2015Publication date: March 30, 2017Inventors: Suchismita Banerjee, Girish G. Kurup, Ashutosh Misra, Niranjan Vaish
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Publication number: 20170093656Abstract: A method for analyzing streaming data includes providing a streaming accumulator comprising an addition module and two multiplexers, receiving one or more data streams, continuously calculating a set of basic statistical elements, receiving a request to calculate a set of statistical descriptors, calculating the set of statistical descriptors, and providing the set of statistical descriptors. An apparatus for analyzing streaming data includes a first multiplexer configured to receive a first summation, a second summation, and a current data item, and forward the first summation on cycles 1 and 3, forward the second summation on cycle 4, and forward the current data item on cycle 2, a second multiplexer configured to receiver the second summation, a third summation, and a previous data item, and forward the previous data item on cycles 1 and 3, forward the second summation on cycle 4, and forward the third summation on cycle 2.Type: ApplicationFiled: July 21, 2016Publication date: March 30, 2017Inventors: Suchismita Banerjee, Girish G. Kurup, Ashutosh Misra, Niranjan Vaish
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Publication number: 20150063348Abstract: A method and system are provided for implementing a hierarchical high radix switch with a time-sliced crossbar. The hierarchical high radix switch includes a plurality of inputs and a plurality of outputs. Each input belongs to one input group; each input group sends consolidated requests to each output, by ORing the requests from the local input ports in that input group. Each output port belongs to one output group; each output port grants one of the requesting input groups using a rotating priority defined by a next-to-serve pointer. Each output group consolidates the output port grants and allows one grant to pass back to an input group. Each input port in an input group evaluates all incoming grants in an oldest packet first manner to form an accept. Each input group consolidates the input port accepts and selects one accept to send to the output port.Type: ApplicationFiled: August 28, 2013Publication date: March 5, 2015Applicant: International Business Machines CorporationInventors: Nikolaos Chrysos, Girish G. Kurup, Cyriel J. Minkenberg, Anil Pothireddy, Mark L. Rudquist, Vibhor K. Srivastava, Brian T. Vanderpool
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Patent number: 7782863Abstract: A method of transmitting data and a data management layer. The method includes: providing a cyclic redundancy check generator connected to a retry buffer through a multiplexer; providing a sequence number generator connected to the retry buffer through the multiplexer; generating a sequence number; generating a sequence number cyclic redundancy check remainder using preset inputs of a cyclic redundancy check remainder latch of the cyclic redundancy check generator; providing an input data bus connected directly to the cyclic redundancy check generator and connected to the retry buffer through the multiplexer; providing an output data bus directly connected to the retry buffer; receiving a data packet on the input data bus; adding the sequence number and the cyclic redundancy check remainder to the data packet to create a modified data packet; storing the modified data packet in the retry buffer; and transmitting the modified data packet using the output data bus.Type: GrantFiled: January 27, 2009Date of Patent: August 24, 2010Assignee: International Business Machines CorporationInventors: Shridhar N. Ambilkar, Girish G. Kurup, Ashutosh Misra