Patents by Inventor Girish K. Singh

Girish K. Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9326371
    Abstract: An information handling system includes a printed circuit board (PCB) including a signal path with a trace coupled to a source, another trace coupled to a load, a tuned stub, and a via connecting the traces and the tuned stub. A method includes providing a signal path on a PCB with a trace coupled to a source, a trace coupled to a load, a tuned stub, and a via connecting the traces and the tuned stub, driving a signal on the signal path, and adjusting the tuned stub length so that the signal is unchanged between the source and the load. A PCB includes a signal path between a source and a load with two traces and a via, and a tuned path between the source and the load with the two traces, another trace, and the via, the length of the tuned path being a half wavelength stub.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: April 26, 2016
    Assignee: DELL PRODUCTS, LP
    Inventors: Sandor T. Farkas, Girish K. Singh
  • Patent number: 7680226
    Abstract: A digital signal waveform receiving circuit may be processed by a non-linear adaptive canonical correlation analysis circuit that may quantify and minimize crosstalk-induced jitter timing skew for improving set-up and hold timing margins of data streams on the receiving circuit. A non-linear adaptive canonical correlation analysis circuit may be placed between an incoming digital signal from a serial link and a PHY receiving layer of an information handling system 100. The PHY receiving layer of the information handling system may be coupled to the non-linear adaptive canonical correlation analysis circuit or may be coupled to the digital signal. This coupling selection may be automatically programmed depending on received signal cross-talk-induced jitter timing skew or may be programmed by a user of the information handling system.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: March 16, 2010
    Assignee: Dell Products L.P.
    Inventors: Rajen Murugan, Girish K. Singh
  • Publication number: 20100064180
    Abstract: An information handling system includes a printed circuit board (PCB) including a signal path with a trace coupled to a source, another trace coupled to a load, a tuned stub, and a via connecting the traces and the tuned stub. A method includes providing a signal path on a PCB with a trace coupled to a source, a trace coupled to a load, a tuned stub, and a via connecting the traces and the tuned stub, driving a signal on the signal path, and adjusting the tuned stub length so that the signal is unchanged between the source and the load. A PCB includes a signal path between a source and a load with two traces and a via, and a tuned path between the source and the load with the two traces, another trace, and the via, the length of the tuned path being a half wavelength stub.
    Type: Application
    Filed: September 10, 2008
    Publication date: March 11, 2010
    Applicant: DELL PRODUCTS, LP
    Inventors: Sandor T. Farkas, Girish K. Singh