Patents by Inventor Girish T P

Girish T P has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DOMAIN MERGER CELL TO ABUT POWER DOMAINS FOR CHIP AREA REDUCTION
    Publication number: 20250072110
    Abstract: A chip includes a merger cell including a first p-type length of diffusion (LOD) region extending in a first direction, a first n-well underneath the first p-type LOD region, a first supply rail configured to receive a first supply voltage, and a first n-tap coupling the first n-well to the first supply rail. The merger cell also includes a second p-type length of diffusion (LOD) region extending in the first direction, a second n-well underneath the second p-type LOD region, a second supply rail configured to receive a second supply voltage different from the first supply voltage, and a second n-tap coupling the second n-well to the second supply rail.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Inventors: Kamesh MEDISETTI, Sharad Kumar GUPTA, Sudesh Chandra SRIVASTAVA, Somesh AGARWAL, Udayakiran Kumar YALLAMARAJU, Anand Ashok BALIGATTI, Girish T P, Ankur MEHROTRA, Gousulu KANDUKURU, Abhinav CHAUHAN, Amit KASHYAP, Parissa NAJDESAMII