Patents by Inventor Girish VARATKAR

Girish VARATKAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Deeply-pipelined high-throughput LDPC decoder architecture
    Patent number: 10778371
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs. Accordingly, aspects of the present disclosure provide techniques for reducing delays in a processing pipeline by, in some cases, relaxing a dependency between updating bit log likelihood ratios (LLRs) and computing a posteriori LLRs.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 15, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Vincent Loncke, Girish Varatkar, Thomas Joseph Richardson, Yi Cao
  • Early termination technique for LDPC decoder architecture
    Patent number: 10312937
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to early termination techniques for low-density parity-check (LDPC) decoder architecture.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: June 4, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Vincent Loncke, Yi Cao, Girish Varatkar
  • EARLY TERMINATION TECHNIQUE FOR LDPC DECODER ARCHITECTURE
    Publication number: 20180123614
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to early termination techniques for low-density parity-check (LDPC) decoder architecture.
    Type: Application
    Filed: June 9, 2017
    Publication date: May 3, 2018
    Inventors: Vincent LONCKE, Yi CAO, Girish VARATKAR
  • DEEPLY-PIPELINED HIGH-THROUGHPUT LDPC DECODER ARCHITECTURE
    Publication number: 20180123734
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs.
    Type: Application
    Filed: September 22, 2017
    Publication date: May 3, 2018
    Inventors: Vincent LONCKE, Girish VARATKAR, Thomas Joseph RICHARDSON, Yi CAO
  • NON-LINEAR LOG-LIKELIHOOD RATIO QUANTIZATION TECHNIQUES FOR LDPC DECODER ARCHITECTURE
    Publication number: 20180123615
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to non-linear log-likelihood ratio quantization techniques for low-density parity-check (LDPC) decoder architecture.
    Type: Application
    Filed: June 9, 2017
    Publication date: May 3, 2018
    Inventors: Girish VARATKAR, Vincent LONCKE, Thomas Joseph RICHARDSON, Yi CAO