Patents by Inventor Girish Venkatasubramanian

Girish Venkatasubramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160085531
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to validate translated guest code in a dynamic binary translator. An example apparatus disclosed herein includes a translator to generate a first translation of code to execute on a host machine, the first translation of the guest code to facilitate creating a first translated guest code, and the translator to generate a second translation of the translated guest code to execute on the host machine. The example apparatus also includes a translation versions manager to identify a first host machine state based on executing a portion of the first translation, and the translation versions manager to identify a second host machine state based on executing a portion of the second translation. The example system also includes a validator to determine a state divergence status of the second translation based on a comparison between the first host machine state and the second host machine state.
    Type: Application
    Filed: December 2, 2015
    Publication date: March 24, 2016
    Inventors: Girish Venkatasubramanian, Chaitanya Mangla, Gerolf F. Hoflehner, Ethan Schuchman
  • Patent number: 9274799
    Abstract: A processor includes a front end and a scheduler. The front end includes logic to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes logic to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: March 1, 2016
    Assignee: Intel Corporation
    Inventors: Sebastian Winkel, Ethan Schuchman, Tyler Sondag, Girish Venkatasubramanian
  • Patent number: 9223553
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to validate translated guest code in a dynamic binary translator. An example apparatus disclosed herein includes a translator to generate a first translation of code to execute on a host machine, the first translation of the guest code to facilitate creating a first translated guest code, and the translator to generate a second translation of the translated guest code to execute on the host machine. The example apparatus also includes a translation versions manager to identify a first host machine state based on executing a portion of the first translation, and the translation versions manager to identify a second host machine state based on executing a portion of the second translation. The example system also includes a validator to determine a state divergence status of the second translation based on a comparison between the first host machine state and the second host machine state.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: December 29, 2015
    Assignee: INTEL CORPORATION
    Inventors: Girish Venkatasubramanian, Chaitanya Mangla, Gerolf F. Hoflehner, Ethan Schuchman
  • Publication number: 20150178104
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to validate translated guest code in a dynamic binary translator. An example apparatus disclosed herein includes a translator to generate a first translation of code to execute on a host machine, the first translation of the guest code to facilitate creating a first translated guest code, and the translator to generate a second translation of the translated guest code to execute on the host machine. The example apparatus also includes a translation versions manager to identify a first host machine state based on executing a portion of the first translation, and the translation versions manager to identify a second host machine state based on executing a portion of the second translation. The example system also includes a validator to determine a state divergence status of the second translation based on a comparison between the first host machine state and the second host machine state.
    Type: Application
    Filed: September 26, 2013
    Publication date: June 25, 2015
    Inventors: Girish Venkatasubramanian, Chaitanya Mangla, Gerolf F. Hoflehner, Ethan Schuchman